Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 1d52512b2e81dbfae2cf11f6ef886bc22a7cd4d8 / . / configs / evb-rk3568_defconfig
blob: 2076f55122befba0ab0eb92ae0d13dca4a04d5bf [file] [log] [blame]
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]1CONFIG_ARM=y
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]2CONFIG_SKIP_LOWLEVEL_INIT=y
Peng Fanc8a61c02022-04-13 17:47:20 +0800[diff] [blame]3CONFIG_COUNTER_FREQUENCY=24000000
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]4CONFIG_ARCH_ROCKCHIP=y
Jonas Karlman737739e2024-05-04 19:43:00 +0000[diff] [blame]5CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-evb1-v10"
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]6CONFIG_ROCKCHIP_RK3568=y
Nico Cheng00ceeb02021-10-26 10:42:19 +0800[diff] [blame]7CONFIG_SPL_SERIAL=y
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]8CONFIG_DEBUG_UART_BASE=0xFE660000
9CONFIG_DEBUG_UART_CLOCK=24000000
Tom Rini0997ee02021-08-23 10:25:31 -0400[diff] [blame]10CONFIG_SYS_LOAD_ADDR=0xc00800
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]11CONFIG_DEBUG_UART=y
Nico Cheng00ceeb02021-10-26 10:42:19 +0800[diff] [blame]12CONFIG_FIT=y
13CONFIG_FIT_VERBOSE=y
Jonas Karlmanfea31cc2023-05-17 18:26:32 +0000[diff] [blame]14CONFIG_SPL_FIT_SIGNATURE=y
Nico Cheng00ceeb02021-10-26 10:42:19 +0800[diff] [blame]15CONFIG_SPL_LOAD_FIT=y
Jonas Karlmanbb5fabe2023-06-26 19:43:06 +0000[diff] [blame]16CONFIG_LEGACY_IMAGE_FORMAT=y
Jonas Karlman737739e2024-05-04 19:43:00 +0000[diff] [blame]17CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb1-v10.dtb"
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]18# CONFIG_DISPLAY_CPUINFO is not set
19CONFIG_DISPLAY_BOARDINFO_LATE=y
Jonas Karlmanfea31cc2023-05-17 18:26:32 +0000[diff] [blame]20CONFIG_SPL_MAX_SIZE=0x40000
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]21CONFIG_SPL_PAD_TO=0x7f8000
Nico Cheng00ceeb02021-10-26 10:42:19 +0800[diff] [blame]22# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Nico Cheng00ceeb02021-10-26 10:42:19 +0800[diff] [blame]23CONFIG_SPL_ATF=y
Jonas Karlmanfea31cc2023-05-17 18:26:32 +0000[diff] [blame]24CONFIG_CMD_GPIO=y
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]25CONFIG_CMD_GPT=y
Jonas Karlmanfea31cc2023-05-17 18:26:32 +0000[diff] [blame]26CONFIG_CMD_I2C=y
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]27CONFIG_CMD_MMC=y
28# CONFIG_CMD_SETEXPR is not set
Jonas Karlmanfea31cc2023-05-17 18:26:32 +0000[diff] [blame]29CONFIG_CMD_PMIC=y
30CONFIG_CMD_REGULATOR=y
Nico Cheng00ceeb02021-10-26 10:42:19 +0800[diff] [blame]31# CONFIG_SPL_DOS_PARTITION is not set
32CONFIG_SPL_OF_CONTROL=y
33CONFIG_OF_LIVE=y
Jonas Karlman5aefcd92024-04-22 06:28:51 +0000[diff] [blame]34CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Jonas Karlmand21f0092023-10-01 19:17:21 +0000[diff] [blame]35CONFIG_SPL_DM_SEQ_ALIAS=y
Nico Cheng00ceeb02021-10-26 10:42:19 +0800[diff] [blame]36CONFIG_SPL_REGMAP=y
37CONFIG_SPL_SYSCON=y
38CONFIG_SPL_CLK=y
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]39CONFIG_ROCKCHIP_GPIO=y
40CONFIG_SYS_I2C_ROCKCHIP=y
41CONFIG_MISC=y
Tom Rini5df873f2021-12-11 14:55:53 -0500[diff] [blame]42CONFIG_SUPPORT_EMMC_RPMB=y
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]43CONFIG_MMC_DW=y
44CONFIG_MMC_DW_ROCKCHIP=y
45CONFIG_MMC_SDHCI=y
46CONFIG_MMC_SDHCI_SDMA=y
47CONFIG_MMC_SDHCI_ROCKCHIP=y
Jonas Karlmand21f0092023-10-01 19:17:21 +0000[diff] [blame]48CONFIG_PHY_REALTEK=y
49CONFIG_DWC_ETH_QOS=y
50CONFIG_DWC_ETH_QOS_ROCKCHIP=y
Jonas Karlman5aefcd92024-04-22 06:28:51 +0000[diff] [blame]51CONFIG_SPL_PINCTRL=y
Jonas Karlmanfea31cc2023-05-17 18:26:32 +0000[diff] [blame]52CONFIG_DM_PMIC=y
53CONFIG_PMIC_RK8XX=y
54CONFIG_REGULATOR_RK8XX=y
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]55CONFIG_PWM_ROCKCHIP=y
Nico Cheng00ceeb02021-10-26 10:42:19 +0800[diff] [blame]56CONFIG_SPL_RAM=y
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]57CONFIG_BAUDRATE=1500000
58CONFIG_DEBUG_UART_SHIFT=2
Tom Rinidc172ee2022-12-04 09:39:03 -0500[diff] [blame]59CONFIG_SYS_NS16550_MEM32=y
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]60CONFIG_SYSRESET=y
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]61CONFIG_ERRNO_STR=y