blob: b794b73b6bd7969f5fd0816397c903ced9c31776 [file] [log] [blame]
Yanhong Wang6a5a45d2023-03-29 11:42:17 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
5 */
6
Yanhong Wang4e321fa2023-06-15 17:36:52 +08007#include <asm/arch/eeprom.h>
Chanho Park9ca68c92023-10-31 17:56:00 +09008#include <asm/arch/gpio.h>
Yanhong Wang6a5a45d2023-03-29 11:42:17 +08009#include <asm/arch/regs.h>
10#include <asm/arch/spl.h>
11#include <asm/io.h>
Yanhong Wang4e321fa2023-06-15 17:36:52 +080012#include <dt-bindings/clock/starfive,jh7110-crg.h>
13#include <fdt_support.h>
14#include <linux/libfdt.h>
Yanhong Wang6a5a45d2023-03-29 11:42:17 +080015#include <log.h>
16#include <spl.h>
17
Yanhong Wang4e321fa2023-06-15 17:36:52 +080018DECLARE_GLOBAL_DATA_PTR;
Yanhong Wang6a5a45d2023-03-29 11:42:17 +080019#define JH7110_CLK_CPU_ROOT_OFFSET 0x0U
20#define JH7110_CLK_CPU_ROOT_SHIFT 24
21#define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24)
22
Yanhong Wang4e321fa2023-06-15 17:36:52 +080023struct starfive_vf2_pro {
24 const char *path;
25 const char *name;
26 const char *value;
27};
28
Heinrich Schuchardtf8841732024-04-02 10:49:10 +020029static const struct starfive_vf2_pro milk_v_mars[] = {
30 {"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL},
31 {"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL},
32
33 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
34 "motorcomm,tx-clk-adj-enabled", NULL},
35 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
36 "motorcomm,tx-clk-100-inverted", NULL},
37 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
38 "motorcomm,tx-clk-1000-inverted", NULL},
39 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
40 "motorcomm,rx-clk-drv-microamp", "3970"},
41 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
42 "motorcomm,rx-data-drv-microamp", "2910"},
43 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
44 "rx-internal-delay-ps", "1900"},
45 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
46 "tx-internal-delay-ps", "1500"},
47};
48
Yanhong Wang4e321fa2023-06-15 17:36:52 +080049static const struct starfive_vf2_pro starfive_vera[] = {
50 {"/soc/ethernet@16030000/mdio/ethernet-phy@0", "rx-internal-delay-ps",
51 "1900"},
52 {"/soc/ethernet@16030000/mdio/ethernet-phy@0", "tx-internal-delay-ps",
53 "1350"}
54};
55
56static const struct starfive_vf2_pro starfive_verb[] = {
57 {"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL},
58 {"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL},
59
60 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
61 "motorcomm,tx-clk-adj-enabled", NULL},
62 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
63 "motorcomm,tx-clk-100-inverted", NULL},
64 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
65 "motorcomm,tx-clk-1000-inverted", NULL},
66 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
Lukasz Tekielia99605d2024-01-28 20:22:48 +010067 "motorcomm,rx-clk-drv-microamp", "3970"},
68 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
69 "motorcomm,rx-data-drv-microamp", "2910"},
70 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
Yanhong Wang4e321fa2023-06-15 17:36:52 +080071 "rx-internal-delay-ps", "1900"},
72 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
73 "tx-internal-delay-ps", "1500"},
74
75 {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
76 "motorcomm,tx-clk-adj-enabled", NULL},
77 { "/soc/ethernet@16040000/mdio/ethernet-phy@1",
78 "motorcomm,tx-clk-100-inverted", NULL},
79 {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
Lukasz Tekielia99605d2024-01-28 20:22:48 +010080 "motorcomm,rx-clk-drv-microamp", "3970"},
81 {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
82 "motorcomm,rx-data-drv-microamp", "2910"},
83 {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
Yanhong Wang4e321fa2023-06-15 17:36:52 +080084 "rx-internal-delay-ps", "0"},
85 {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
86 "tx-internal-delay-ps", "0"},
87};
88
H Bell25ce7c92024-05-22 19:12:48 +000089static const struct starfive_vf2_pro star64_pine64[] = {
90 {"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL},
91 {"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL},
92
93 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
94 "motorcomm,tx-clk-adj-enabled", NULL},
95 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
96 "motorcomm,tx-clk-10-inverted", NULL},
97 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
98 "motorcomm,tx-clk-100-inverted", NULL},
99 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
100 "motorcomm,tx-clk-1000-inverted", NULL},
101 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
102 "motorcomm,rx-clk-drv-microamp", "2910"},
103 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
104 "motorcomm,rx-data-drv-microamp", "2910"},
105 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
106 "rx-internal-delay-ps", "1900"},
107 {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
108 "tx-internal-delay-ps", "1500"},
109
110 {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
111 "motorcomm,tx-clk-adj-enabled", NULL},
112 {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
113 "motorcomm,tx-clk-10-inverted", NULL},
114 {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
115 "motorcomm,tx-clk-100-inverted", NULL},
116 {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
117 "motorcomm,rx-clk-drv-microamp", "2910"},
118 {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
119 "motorcomm,rx-data-drv-microamp", "2910"},
120 {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
121 "rx-internal-delay-ps", "0"},
122 {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
123 "tx-internal-delay-ps", "300"},
124};
125
Heinrich Schuchardtf8841732024-04-02 10:49:10 +0200126void spl_fdt_fixup_mars(void *fdt)
127{
128 static const char compat[] = "milkv,mars\0starfive,jh7110";
129 u32 phandle;
130 u8 i;
131 int offset;
132 int ret;
133
134 fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
135 fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
136 "Milk-V Mars");
137
138 /* gmac0 */
139 offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000");
140 phandle = fdt_get_phandle(fdt, offset);
141 offset = fdt_path_offset(fdt, "/soc/ethernet@16030000");
142
143 fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
144 fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX);
145 fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
146 fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
147 JH7110_AONCLK_GMAC0_RMII_RTX);
148
149 /* gmac1 */
150 fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@16040000"),
151 "status", "disabled");
152
153 for (i = 0; i < ARRAY_SIZE(milk_v_mars); i++) {
154 offset = fdt_path_offset(fdt, milk_v_mars[i].path);
155
156 if (milk_v_mars[i].value)
157 ret = fdt_setprop_u32(fdt, offset, milk_v_mars[i].name,
158 dectoul(milk_v_mars[i].value, NULL));
159 else
160 ret = fdt_setprop_empty(fdt, offset, milk_v_mars[i].name);
161
162 if (ret) {
163 pr_err("%s set prop %s fail.\n", __func__, milk_v_mars[i].name);
164 break;
165 }
166 }
167}
168
Heinrich Schuchardtadaa12d2024-05-12 06:25:23 +0200169void spl_fdt_fixup_mars_cm(void *fdt)
170{
171 const char *compat;
172 const char *model;
173
174 spl_fdt_fixup_mars(fdt);
175
176 if (!get_mmc_size_from_eeprom()) {
177 int offset;
178
179 model = "Milk-V Mars CM Lite";
180 compat = "milkv,mars-cm-lite\0starfive,jh7110";
181
182 offset = fdt_path_offset(fdt, "/soc/pinctrl/mmc0-pins/mmc0-pins-rest");
183 /* GPIOMUX(22, GPOUT_SYS_SDIO0_RST, GPOEN_ENABLE, GPI_NONE) */
184 fdt_setprop_u32(fdt, offset, "pinmux", 0xff130016);
185 } else {
186 model = "Milk-V Mars CM";
187 compat = "milkv,mars-cm\0starfive,jh7110";
188 }
189 fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
190 fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", model);
191}
192
Yanhong Wang4e321fa2023-06-15 17:36:52 +0800193void spl_fdt_fixup_version_a(void *fdt)
194{
Aurelien Jarno5acb7c12024-01-10 21:17:44 +0100195 static const char compat[] = "starfive,visionfive-2-v1.2a\0starfive,jh7110";
Yanhong Wang4e321fa2023-06-15 17:36:52 +0800196 u32 phandle;
197 u8 i;
198 int offset;
199 int ret;
200
Aurelien Jarno5acb7c12024-01-10 21:17:44 +0100201 fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
Yanhong Wang4e321fa2023-06-15 17:36:52 +0800202 fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
203 "StarFive VisionFive 2 v1.2A");
204
205 offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000");
206 phandle = fdt_get_phandle(fdt, offset);
207 offset = fdt_path_offset(fdt, "/soc/ethernet@16040000");
208
209 fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
210 fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX);
211 fdt_appendprop_u32(fdt, offset, "assigned-clocks", phandle);
212 fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_RX);
213
214 fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
215 fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
216 JH7110_SYSCLK_GMAC1_RMII_RTX);
217 fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", phandle);
218 fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
219 JH7110_SYSCLK_GMAC1_RMII_RTX);
220
221 fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@16040000"),
222 "phy-mode", "rmii");
223
224 for (i = 0; i < ARRAY_SIZE(starfive_vera); i++) {
225 offset = fdt_path_offset(fdt, starfive_vera[i].path);
226
227 if (starfive_vera[i].value)
228 ret = fdt_setprop_u32(fdt, offset, starfive_vera[i].name,
229 dectoul(starfive_vera[i].value, NULL));
230 else
231 ret = fdt_setprop_empty(fdt, offset, starfive_vera[i].name);
232
233 if (ret) {
234 pr_err("%s set prop %s fail.\n", __func__, starfive_vera[i].name);
235 break;
236 }
237 }
238}
239
240void spl_fdt_fixup_version_b(void *fdt)
241{
Aurelien Jarno5acb7c12024-01-10 21:17:44 +0100242 static const char compat[] = "starfive,visionfive-2-v1.3b\0starfive,jh7110";
Yanhong Wang4e321fa2023-06-15 17:36:52 +0800243 u32 phandle;
244 u8 i;
245 int offset;
246 int ret;
247
Aurelien Jarno5acb7c12024-01-10 21:17:44 +0100248 fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
Yanhong Wang4e321fa2023-06-15 17:36:52 +0800249 fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
250 "StarFive VisionFive 2 v1.3B");
251
252 /* gmac0 */
253 offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000");
254 phandle = fdt_get_phandle(fdt, offset);
255 offset = fdt_path_offset(fdt, "/soc/ethernet@16030000");
256
257 fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
258 fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX);
259 fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
260 fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
261 JH7110_AONCLK_GMAC0_RMII_RTX);
262
263 /* gmac1 */
264 offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000");
265 phandle = fdt_get_phandle(fdt, offset);
266 offset = fdt_path_offset(fdt, "/soc/ethernet@16040000");
267
268 fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
269 fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX);
270 fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
271 fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
272 JH7110_SYSCLK_GMAC1_RMII_RTX);
273
274 for (i = 0; i < ARRAY_SIZE(starfive_verb); i++) {
275 offset = fdt_path_offset(fdt, starfive_verb[i].path);
276
277 if (starfive_verb[i].value)
278 ret = fdt_setprop_u32(fdt, offset, starfive_verb[i].name,
279 dectoul(starfive_verb[i].value, NULL));
280 else
281 ret = fdt_setprop_empty(fdt, offset, starfive_verb[i].name);
282
283 if (ret) {
284 pr_err("%s set prop %s fail.\n", __func__, starfive_verb[i].name);
285 break;
286 }
287 }
288}
289
H Bell25ce7c92024-05-22 19:12:48 +0000290void spl_fdt_fixup_star64(void *fdt)
291{
292 static const char compat[] = "pine64,star64\0starfive,jh7110";
293 u32 phandle;
294 u8 i;
295 int offset;
296 int ret;
297
298 fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
299 fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
300 "Pine64 Star64");
301
302 /* gmac0 */
303 offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000");
304 phandle = fdt_get_phandle(fdt, offset);
305 offset = fdt_path_offset(fdt, "/soc/ethernet@16030000");
306
307 fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
308 fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX);
309 fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
310 fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
311 JH7110_AONCLK_GMAC0_RMII_RTX);
312
313 /* gmac1 */
314 offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000");
315 phandle = fdt_get_phandle(fdt, offset);
316 offset = fdt_path_offset(fdt, "/soc/ethernet@16040000");
317
318 fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
319 fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX);
320 fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
321 fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
322 JH7110_SYSCLK_GMAC1_RMII_RTX);
323
324 for (i = 0; i < ARRAY_SIZE(star64_pine64); i++) {
325 offset = fdt_path_offset(fdt, star64_pine64[i].path);
326
327 if (star64_pine64[i].value)
328 ret = fdt_setprop_u32(fdt, offset, star64_pine64[i].name,
329 dectoul(star64_pine64[i].value, NULL));
330 else
331 ret = fdt_setprop_empty(fdt, offset, star64_pine64[i].name);
332
333 if (ret) {
334 pr_err("%s set prop %s fail.\n", __func__, star64_pine64[i].name);
335 break;
336 }
337 }
338}
339
Yanhong Wang4e321fa2023-06-15 17:36:52 +0800340void spl_perform_fixups(struct spl_image_info *spl_image)
341{
342 u8 version;
Heinrich Schuchardtf8841732024-04-02 10:49:10 +0200343 const char *product_id;
Yanhong Wang4e321fa2023-06-15 17:36:52 +0800344
Heinrich Schuchardtf8841732024-04-02 10:49:10 +0200345 product_id = get_product_id_from_eeprom();
346 if (!product_id) {
347 pr_err("Can't read EEPROM\n");
348 return;
349 }
Heinrich Schuchardtadaa12d2024-05-12 06:25:23 +0200350 if (!strncmp(product_id, "MARC", 4)) {
351 spl_fdt_fixup_mars_cm(spl_image->fdt_addr);
352 } else if (!strncmp(product_id, "MARS", 4)) {
Heinrich Schuchardtf8841732024-04-02 10:49:10 +0200353 spl_fdt_fixup_mars(spl_image->fdt_addr);
354 } else if (!strncmp(product_id, "VF7110", 6)) {
355 version = get_pcb_revision_from_eeprom();
356 switch (version) {
357 case 'a':
358 case 'A':
359 spl_fdt_fixup_version_a(spl_image->fdt_addr);
360 break;
Yanhong Wang4e321fa2023-06-15 17:36:52 +0800361
Heinrich Schuchardtf8841732024-04-02 10:49:10 +0200362 case 'b':
363 case 'B':
364 default:
365 spl_fdt_fixup_version_b(spl_image->fdt_addr);
Yanhong Wang4e321fa2023-06-15 17:36:52 +0800366 break;
Heinrich Schuchardtf8841732024-04-02 10:49:10 +0200367 };
H Bell25ce7c92024-05-22 19:12:48 +0000368 } else if (!strncmp(product_id, "STAR64", 6)) {
369 spl_fdt_fixup_star64(spl_image->fdt_addr);
Heinrich Schuchardtf8841732024-04-02 10:49:10 +0200370 } else {
371 pr_err("Unknown product %s\n", product_id);
Yanhong Wang4e321fa2023-06-15 17:36:52 +0800372 };
373
Heinrich Schuchardtf8841732024-04-02 10:49:10 +0200374 /* Update the memory size which read from eeprom or DT */
Yanhong Wang4e321fa2023-06-15 17:36:52 +0800375 fdt_fixup_memory(spl_image->fdt_addr, 0x40000000, gd->ram_size);
376}
Chanho Park9ca68c92023-10-31 17:56:00 +0900377
378static void jh7110_jtag_init(void)
379{
380 /* nTRST: GPIO36 */
381 SYS_IOMUX_DOEN(36, HIGH);
382 SYS_IOMUX_DIN(36, 4);
383 /* TDI: GPIO61 */
384 SYS_IOMUX_DOEN(61, HIGH);
385 SYS_IOMUX_DIN(61, 19);
386 /* TMS: GPIO63 */
387 SYS_IOMUX_DOEN(63, HIGH);
388 SYS_IOMUX_DIN(63, 20);
389 /* TCK: GPIO60 */
390 SYS_IOMUX_DOEN(60, HIGH);
391 SYS_IOMUX_DIN(60, 29);
392 /* TDO: GPIO44 */
393 SYS_IOMUX_DOEN(44, 8);
394 SYS_IOMUX_DOUT(44, 22);
395}
396
Yanhong Wang6a5a45d2023-03-29 11:42:17 +0800397int spl_board_init_f(void)
398{
399 int ret;
400
Chanho Park9ca68c92023-10-31 17:56:00 +0900401 jh7110_jtag_init();
402
Lukas Funke2b62dd62024-04-24 09:43:39 +0200403 ret = spl_dram_init();
Yanhong Wang6a5a45d2023-03-29 11:42:17 +0800404 if (ret) {
Lukas Funke2b62dd62024-04-24 09:43:39 +0200405 debug("JH7110 DRAM init failed: %d\n", ret);
Yanhong Wang6a5a45d2023-03-29 11:42:17 +0800406 return ret;
407 }
408
409 return 0;
410}
411
412u32 spl_boot_device(void)
413{
414 u32 mode;
415
416 mode = in_le32(JH7110_BOOT_MODE_SELECT_REG)
417 & JH7110_BOOT_MODE_SELECT_MASK;
418 switch (mode) {
419 case 0:
420 return BOOT_DEVICE_SPI;
421
422 case 1:
423 return BOOT_DEVICE_MMC2;
424
425 case 2:
426 return BOOT_DEVICE_MMC1;
427
428 case 3:
429 return BOOT_DEVICE_UART;
430
431 default:
432 debug("Unsupported boot device 0x%x.\n", mode);
433 return BOOT_DEVICE_NONE;
434 }
435}
436
437void board_init_f(ulong dummy)
438{
439 int ret;
440
441 ret = spl_early_init();
442 if (ret)
443 panic("spl_early_init() failed: %d\n", ret);
444
Simon Glassb8357c12023-08-21 21:16:56 -0600445 riscv_cpu_setup();
Yanhong Wang6a5a45d2023-03-29 11:42:17 +0800446 preloader_console_init();
447
448 /* Set the parent clock of cpu_root clock to pll0,
449 * it must be initialized here
450 */
451 clrsetbits_le32(JH7110_SYS_CRG + JH7110_CLK_CPU_ROOT_OFFSET,
452 JH7110_CLK_CPU_ROOT_MASK,
453 BIT(JH7110_CLK_CPU_ROOT_SHIFT));
454
455 ret = spl_board_init_f();
456 if (ret) {
457 debug("spl_board_init_f init failed: %d\n", ret);
458 return;
459 }
460}
461
462#if CONFIG_IS_ENABLED(SPL_LOAD_FIT)
463int board_fit_config_name_match(const char *name)
464{
465 /* boot using first FIT config */
466 return 0;
467}
468#endif