blob: 666514220312f69a50a425e1eebecccabaff5232 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Shengzhou Liu07886942013-11-22 17:39:11 +08002/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
Shengzhou Liu07886942013-11-22 17:39:11 +08004 */
5
Shengzhou Liu031228a2014-02-21 13:16:19 +08006#ifndef __T208xQDS_QIXIS_H__
7#define __T208xQDS_QIXIS_H__
Shengzhou Liu07886942013-11-22 17:39:11 +08008
Shengzhou Liu031228a2014-02-21 13:16:19 +08009/* Definitions of QIXIS Registers for T208xQDS */
Shengzhou Liu07886942013-11-22 17:39:11 +080010
11#define QIXIS_SRDS1CLK_122 0x5a
12#define QIXIS_SRDS1CLK_125 0x5e
13
Shengzhou Liu07886942013-11-22 17:39:11 +080014/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
15#define BRDCFG4_EMISEL_MASK 0xE0
16#define BRDCFG4_EMISEL_SHIFT 5
17
18/* SYSCLK */
19#define QIXIS_SYSCLK_66 0x0
20#define QIXIS_SYSCLK_83 0x1
21#define QIXIS_SYSCLK_100 0x2
22#define QIXIS_SYSCLK_125 0x3
23#define QIXIS_SYSCLK_133 0x4
24#define QIXIS_SYSCLK_150 0x5
25#define QIXIS_SYSCLK_160 0x6
26#define QIXIS_SYSCLK_166 0x7
27
28/* DDRCLK */
29#define QIXIS_DDRCLK_66 0x0
30#define QIXIS_DDRCLK_100 0x1
31#define QIXIS_DDRCLK_125 0x2
32#define QIXIS_DDRCLK_133 0x3
33
34#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */
35
Shengzhou Liu031228a2014-02-21 13:16:19 +080036#define BRDCFG9_SFP_TX_EN 0x10
37
Shengzhou Liu07886942013-11-22 17:39:11 +080038#define BRDCFG12_SD3EN_MASK 0x20
39#define BRDCFG12_SD3MX_MASK 0x08
40#define BRDCFG12_SD3MX_SLOT5 0x08
41#define BRDCFG12_SD3MX_SLOT6 0x00
42#define BRDCFG12_SD4EN_MASK 0x04
43#define BRDCFG12_SD4MX_MASK 0x03
44#define BRDCFG12_SD4MX_SLOT7 0x02
45#define BRDCFG12_SD4MX_SLOT8 0x01
46#define BRDCFG12_SD4MX_AURO_SATA 0x00
47#endif