Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2010-2011 Freescale Semiconductor, Inc. |
Biwen Li | 6a2d8d1 | 2020-05-01 20:04:13 +0800 | [diff] [blame] | 4 | * Copyright 2020 NXP |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 7 | #include <config.h> |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 8 | #include <command.h> |
Simon Glass | 2dc9c34 | 2020-05-10 11:40:01 -0600 | [diff] [blame] | 9 | #include <image.h> |
Simon Glass | a7b5130 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 10 | #include <init.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 11 | #include <net.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 12 | #include <asm/global_data.h> |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 13 | #include <asm/processor.h> |
| 14 | #include <asm/mmu.h> |
| 15 | #include <asm/cache.h> |
| 16 | #include <asm/immap_85xx.h> |
| 17 | #include <asm/io.h> |
Simon Glass | 0af6e2d | 2019-08-01 09:46:52 -0600 | [diff] [blame] | 18 | #include <env.h> |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 19 | #include <miiphy.h> |
Masahiro Yamada | 75f82d0 | 2018-03-05 01:20:11 +0900 | [diff] [blame] | 20 | #include <linux/libfdt.h> |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 21 | #include <fdt_support.h> |
| 22 | #include <fsl_mdio.h> |
| 23 | #include <tsec.h> |
| 24 | #include <mmc.h> |
| 25 | #include <netdev.h> |
| 26 | #include <pci.h> |
| 27 | #include <asm/fsl_serdes.h> |
York Sun | 37562f6 | 2013-10-22 12:39:02 -0700 | [diff] [blame] | 28 | #include <fsl_ifc.h> |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 29 | #include <asm/fsl_pci.h> |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 30 | #include <hwconfig.h> |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 31 | #include <i2c.h> |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 32 | |
| 33 | DECLARE_GLOBAL_DATA_PTR; |
| 34 | |
| 35 | #define GPIO4_PCIE_RESET_SET 0x08000000 |
| 36 | #define MUX_CPLD_CAN_UART 0x00 |
| 37 | #define MUX_CPLD_TDM 0x01 |
| 38 | #define MUX_CPLD_SPICS0_FLASH 0x00 |
| 39 | #define MUX_CPLD_SPICS0_SLIC 0x02 |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 40 | #define PMUXCR1_IFC_MASK 0x00ffff00 |
| 41 | #define PMUXCR1_SDHC_MASK 0x00fff000 |
| 42 | #define PMUXCR1_SDHC_ENABLE 0x00555000 |
| 43 | |
| 44 | enum { |
| 45 | MUX_TYPE_IFC, |
| 46 | MUX_TYPE_SDHC, |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 47 | MUX_TYPE_SPIFLASH, |
| 48 | MUX_TYPE_TDM, |
| 49 | MUX_TYPE_CAN, |
| 50 | MUX_TYPE_CS0_NOR, |
| 51 | MUX_TYPE_CS0_NAND, |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 52 | }; |
| 53 | |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 54 | enum { |
| 55 | I2C_READ_BANK, |
| 56 | I2C_READ_PCB_VER, |
| 57 | }; |
| 58 | |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 59 | static uint sd_ifc_mux; |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 60 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 61 | struct cpld_data { |
| 62 | u8 cpld_ver; /* cpld revision */ |
York Sun | 7f945ca | 2016-11-16 13:30:06 -0800 | [diff] [blame] | 63 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 64 | u8 pcba_ver; /* pcb revision number */ |
| 65 | u8 twindie_ddr3; |
| 66 | u8 res1[6]; |
| 67 | u8 bank_sel; /* NOR Flash bank */ |
| 68 | u8 res2[5]; |
| 69 | u8 usb2_sel; |
| 70 | u8 res3[1]; |
| 71 | u8 porsw_sel; |
| 72 | u8 tdm_can_sel; |
| 73 | u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */ |
| 74 | u8 por0; /* POR Options */ |
| 75 | u8 por1; /* POR Options */ |
| 76 | u8 por2; /* POR Options */ |
| 77 | u8 por3; /* POR Options */ |
York Sun | 7f945ca | 2016-11-16 13:30:06 -0800 | [diff] [blame] | 78 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 79 | u8 rom_loc; |
| 80 | #endif |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 81 | }; |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 82 | |
| 83 | int board_early_init_f(void) |
| 84 | { |
Tom Rini | d5c3bf2 | 2022-10-28 20:27:12 -0400 | [diff] [blame] | 85 | ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 86 | struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 87 | /* Clock configuration to access CPLD using IFC(GPCM) */ |
Jaiprakash Singh | dd88806 | 2015-03-20 19:28:27 -0700 | [diff] [blame] | 88 | setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 89 | /* |
| 90 | * Reset PCIe slots via GPIO4 |
| 91 | */ |
| 92 | setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET); |
| 93 | setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET); |
| 94 | |
| 95 | return 0; |
| 96 | } |
| 97 | |
| 98 | int board_early_init_r(void) |
| 99 | { |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 100 | const unsigned int flashbase = CFG_SYS_FLASH_BASE; |
York Sun | 220c346 | 2014-06-24 21:16:20 -0700 | [diff] [blame] | 101 | int flash_esel = find_tlb_idx((void *)flashbase, 1); |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 102 | |
| 103 | /* |
| 104 | * Remap Boot flash region to caching-inhibited |
| 105 | * so that flash can be erased properly. |
| 106 | */ |
| 107 | |
| 108 | /* Flush d-cache and invalidate i-cache of any FLASH data */ |
| 109 | flush_dcache(); |
| 110 | invalidate_icache(); |
| 111 | |
York Sun | 220c346 | 2014-06-24 21:16:20 -0700 | [diff] [blame] | 112 | if (flash_esel == -1) { |
| 113 | /* very unlikely unless something is messed up */ |
| 114 | puts("Error: Could not find TLB for FLASH BASE\n"); |
| 115 | flash_esel = 2; /* give our best effort to continue */ |
| 116 | } else { |
| 117 | /* invalidate existing TLB entry for flash */ |
| 118 | disable_tlb(flash_esel); |
| 119 | } |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 120 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 121 | set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 122 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 123 | 0, flash_esel, BOOKE_PAGESZ_16M, 1); |
| 124 | |
| 125 | set_tlb(1, flashbase + 0x1000000, |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 126 | CFG_SYS_FLASH_BASE_PHYS + 0x1000000, |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 127 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 128 | 0, flash_esel+1, BOOKE_PAGESZ_16M, 1); |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 129 | return 0; |
| 130 | } |
| 131 | |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 132 | int config_board_mux(int ctrl_type) |
| 133 | { |
Tom Rini | d5c3bf2 | 2022-10-28 20:27:12 -0400 | [diff] [blame] | 134 | ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 135 | u8 tmp; |
| 136 | |
Igor Opaniuk | f7c9176 | 2021-02-09 13:52:45 +0200 | [diff] [blame] | 137 | #if CONFIG_IS_ENABLED(DM_I2C) |
Biwen Li | 6a2d8d1 | 2020-05-01 20:04:13 +0800 | [diff] [blame] | 138 | struct udevice *dev; |
| 139 | int ret; |
York Sun | 7f945ca | 2016-11-16 13:30:06 -0800 | [diff] [blame] | 140 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 141 | struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 142 | |
Biwen Li | 6a2d8d1 | 2020-05-01 20:04:13 +0800 | [diff] [blame] | 143 | ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, |
| 144 | I2C_PCA9557_ADDR1, 1, &dev); |
| 145 | if (ret) { |
| 146 | printf("%s: Cannot find udev for a bus %d\n", |
| 147 | __func__, I2C_PCA9557_BUS_NUM); |
| 148 | return ret; |
| 149 | } |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 150 | switch (ctrl_type) { |
| 151 | case MUX_TYPE_IFC: |
Biwen Li | 6a2d8d1 | 2020-05-01 20:04:13 +0800 | [diff] [blame] | 152 | tmp = 0xf0; |
| 153 | dm_i2c_write(dev, 3, &tmp, 1); |
| 154 | tmp = 0x01; |
| 155 | dm_i2c_write(dev, 1, &tmp, 1); |
| 156 | sd_ifc_mux = MUX_TYPE_IFC; |
| 157 | clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); |
| 158 | break; |
| 159 | case MUX_TYPE_SDHC: |
| 160 | tmp = 0xf0; |
| 161 | dm_i2c_write(dev, 3, &tmp, 1); |
| 162 | tmp = 0x05; |
| 163 | dm_i2c_write(dev, 1, &tmp, 1); |
| 164 | sd_ifc_mux = MUX_TYPE_SDHC; |
| 165 | clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, |
| 166 | PMUXCR1_SDHC_ENABLE); |
| 167 | break; |
| 168 | case MUX_TYPE_SPIFLASH: |
| 169 | out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); |
| 170 | break; |
| 171 | case MUX_TYPE_TDM: |
| 172 | out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); |
| 173 | out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); |
| 174 | break; |
| 175 | case MUX_TYPE_CAN: |
| 176 | out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); |
| 177 | break; |
| 178 | default: |
| 179 | break; |
| 180 | } |
| 181 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
| 182 | ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, |
| 183 | I2C_PCA9557_ADDR2, 1, &dev); |
| 184 | if (ret) { |
| 185 | printf("%s: Cannot find udev for a bus %d\n", |
| 186 | __func__, I2C_PCA9557_BUS_NUM); |
| 187 | return ret; |
| 188 | } |
| 189 | switch (ctrl_type) { |
| 190 | case MUX_TYPE_IFC: |
| 191 | dm_i2c_read(dev, 0, &tmp, 1); |
| 192 | clrbits_8(&tmp, 0x04); |
| 193 | dm_i2c_write(dev, 1, &tmp, 1); |
| 194 | dm_i2c_read(dev, 3, &tmp, 1); |
| 195 | clrbits_8(&tmp, 0x04); |
| 196 | dm_i2c_write(dev, 3, &tmp, 1); |
| 197 | sd_ifc_mux = MUX_TYPE_IFC; |
| 198 | clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); |
| 199 | break; |
| 200 | case MUX_TYPE_SDHC: |
| 201 | dm_i2c_read(dev, 0, &tmp, 1); |
| 202 | setbits_8(&tmp, 0x04); |
| 203 | dm_i2c_write(dev, 1, &tmp, 1); |
| 204 | dm_i2c_read(dev, 3, &tmp, 1); |
| 205 | clrbits_8(&tmp, 0x04); |
| 206 | dm_i2c_write(dev, 3, &tmp, 1); |
| 207 | sd_ifc_mux = MUX_TYPE_SDHC; |
| 208 | clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, |
| 209 | PMUXCR1_SDHC_ENABLE); |
| 210 | break; |
| 211 | case MUX_TYPE_SPIFLASH: |
| 212 | dm_i2c_read(dev, 0, &tmp, 1); |
| 213 | clrbits_8(&tmp, 0x80); |
| 214 | dm_i2c_write(dev, 1, &tmp, 1); |
| 215 | dm_i2c_read(dev, 3, &tmp, 1); |
| 216 | clrbits_8(&tmp, 0x80); |
| 217 | dm_i2c_write(dev, 3, &tmp, 1); |
| 218 | break; |
| 219 | case MUX_TYPE_TDM: |
| 220 | dm_i2c_read(dev, 0, &tmp, 1); |
| 221 | setbits_8(&tmp, 0x82); |
| 222 | dm_i2c_write(dev, 1, &tmp, 1); |
| 223 | dm_i2c_read(dev, 3, &tmp, 1); |
| 224 | clrbits_8(&tmp, 0x82); |
| 225 | dm_i2c_write(dev, 3, &tmp, 1); |
| 226 | break; |
| 227 | case MUX_TYPE_CAN: |
| 228 | dm_i2c_read(dev, 0, &tmp, 1); |
| 229 | clrbits_8(&tmp, 0x02); |
| 230 | dm_i2c_write(dev, 1, &tmp, 1); |
| 231 | dm_i2c_read(dev, 3, &tmp, 1); |
| 232 | clrbits_8(&tmp, 0x02); |
| 233 | dm_i2c_write(dev, 3, &tmp, 1); |
| 234 | break; |
| 235 | case MUX_TYPE_CS0_NOR: |
| 236 | dm_i2c_read(dev, 0, &tmp, 1); |
| 237 | clrbits_8(&tmp, 0x08); |
| 238 | dm_i2c_write(dev, 1, &tmp, 1); |
| 239 | dm_i2c_read(dev, 3, &tmp, 1); |
| 240 | clrbits_8(&tmp, 0x08); |
| 241 | dm_i2c_write(dev, 3, &tmp, 1); |
| 242 | break; |
| 243 | case MUX_TYPE_CS0_NAND: |
| 244 | dm_i2c_read(dev, 0, &tmp, 1); |
| 245 | setbits_8(&tmp, 0x08); |
| 246 | dm_i2c_write(dev, 1, &tmp, 1); |
| 247 | dm_i2c_read(dev, 3, &tmp, 1); |
| 248 | clrbits_8(&tmp, 0x08); |
| 249 | dm_i2c_write(dev, 3, &tmp, 1); |
| 250 | break; |
| 251 | default: |
| 252 | break; |
| 253 | } |
| 254 | #endif |
| 255 | #else |
| 256 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 257 | struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); |
Biwen Li | 6a2d8d1 | 2020-05-01 20:04:13 +0800 | [diff] [blame] | 258 | |
| 259 | switch (ctrl_type) { |
| 260 | case MUX_TYPE_IFC: |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 261 | i2c_set_bus_num(I2C_PCA9557_BUS_NUM); |
| 262 | tmp = 0xf0; |
| 263 | i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1); |
| 264 | tmp = 0x01; |
| 265 | i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1); |
| 266 | sd_ifc_mux = MUX_TYPE_IFC; |
| 267 | clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); |
| 268 | break; |
| 269 | case MUX_TYPE_SDHC: |
| 270 | i2c_set_bus_num(I2C_PCA9557_BUS_NUM); |
| 271 | tmp = 0xf0; |
| 272 | i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1); |
| 273 | tmp = 0x05; |
| 274 | i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1); |
| 275 | sd_ifc_mux = MUX_TYPE_SDHC; |
| 276 | clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, |
| 277 | PMUXCR1_SDHC_ENABLE); |
| 278 | break; |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 279 | case MUX_TYPE_SPIFLASH: |
| 280 | out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); |
| 281 | break; |
| 282 | case MUX_TYPE_TDM: |
| 283 | out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); |
| 284 | out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); |
| 285 | break; |
| 286 | case MUX_TYPE_CAN: |
| 287 | out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); |
| 288 | break; |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 289 | default: |
| 290 | break; |
| 291 | } |
York Sun | 7f945ca | 2016-11-16 13:30:06 -0800 | [diff] [blame] | 292 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 293 | uint orig_bus = i2c_get_bus_num(); |
| 294 | i2c_set_bus_num(I2C_PCA9557_BUS_NUM); |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 295 | |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 296 | switch (ctrl_type) { |
| 297 | case MUX_TYPE_IFC: |
| 298 | i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); |
| 299 | clrbits_8(&tmp, 0x04); |
| 300 | i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); |
| 301 | i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); |
| 302 | clrbits_8(&tmp, 0x04); |
| 303 | i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); |
| 304 | sd_ifc_mux = MUX_TYPE_IFC; |
| 305 | clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); |
| 306 | break; |
| 307 | case MUX_TYPE_SDHC: |
| 308 | i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); |
| 309 | setbits_8(&tmp, 0x04); |
| 310 | i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); |
| 311 | i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); |
| 312 | clrbits_8(&tmp, 0x04); |
| 313 | i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); |
| 314 | sd_ifc_mux = MUX_TYPE_SDHC; |
| 315 | clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, |
| 316 | PMUXCR1_SDHC_ENABLE); |
| 317 | break; |
| 318 | case MUX_TYPE_SPIFLASH: |
| 319 | i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); |
| 320 | clrbits_8(&tmp, 0x80); |
| 321 | i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); |
| 322 | i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); |
| 323 | clrbits_8(&tmp, 0x80); |
| 324 | i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); |
| 325 | break; |
| 326 | case MUX_TYPE_TDM: |
| 327 | i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); |
| 328 | setbits_8(&tmp, 0x82); |
| 329 | i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); |
| 330 | i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); |
| 331 | clrbits_8(&tmp, 0x82); |
| 332 | i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); |
| 333 | break; |
| 334 | case MUX_TYPE_CAN: |
| 335 | i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); |
| 336 | clrbits_8(&tmp, 0x02); |
| 337 | i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); |
| 338 | i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); |
| 339 | clrbits_8(&tmp, 0x02); |
| 340 | i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); |
| 341 | break; |
| 342 | case MUX_TYPE_CS0_NOR: |
| 343 | i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); |
| 344 | clrbits_8(&tmp, 0x08); |
| 345 | i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); |
| 346 | i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); |
| 347 | clrbits_8(&tmp, 0x08); |
| 348 | i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); |
| 349 | break; |
| 350 | case MUX_TYPE_CS0_NAND: |
| 351 | i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); |
| 352 | setbits_8(&tmp, 0x08); |
| 353 | i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); |
| 354 | i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); |
| 355 | clrbits_8(&tmp, 0x08); |
| 356 | i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); |
| 357 | break; |
| 358 | default: |
| 359 | break; |
| 360 | } |
| 361 | i2c_set_bus_num(orig_bus); |
| 362 | #endif |
Biwen Li | 6a2d8d1 | 2020-05-01 20:04:13 +0800 | [diff] [blame] | 363 | #endif |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 364 | return 0; |
| 365 | } |
| 366 | |
York Sun | 7f945ca | 2016-11-16 13:30:06 -0800 | [diff] [blame] | 367 | #ifdef CONFIG_TARGET_P1010RDB_PB |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 368 | int i2c_pca9557_read(int type) |
| 369 | { |
| 370 | u8 val; |
Biwen Li | 6a2d8d1 | 2020-05-01 20:04:13 +0800 | [diff] [blame] | 371 | int bus_num = I2C_PCA9557_BUS_NUM; |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 372 | |
Igor Opaniuk | f7c9176 | 2021-02-09 13:52:45 +0200 | [diff] [blame] | 373 | #if CONFIG_IS_ENABLED(DM_I2C) |
Biwen Li | 6a2d8d1 | 2020-05-01 20:04:13 +0800 | [diff] [blame] | 374 | struct udevice *dev; |
| 375 | int ret; |
| 376 | |
| 377 | ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2, 1, &dev); |
| 378 | if (ret) { |
| 379 | printf("%s: Cannot find udev for a bus %d\n", |
| 380 | __func__, bus_num); |
| 381 | return ret; |
| 382 | } |
| 383 | dm_i2c_read(dev, 0, &val, 1); |
| 384 | #else |
| 385 | i2c_set_bus_num(bus_num); |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 386 | i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1); |
Biwen Li | 6a2d8d1 | 2020-05-01 20:04:13 +0800 | [diff] [blame] | 387 | #endif |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 388 | |
| 389 | switch (type) { |
| 390 | case I2C_READ_BANK: |
| 391 | val = (val & 0x10) >> 4; |
| 392 | break; |
| 393 | case I2C_READ_PCB_VER: |
| 394 | val = ((val & 0x60) >> 5) + 1; |
| 395 | break; |
| 396 | default: |
| 397 | break; |
| 398 | } |
| 399 | |
| 400 | return val; |
| 401 | } |
| 402 | #endif |
| 403 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 404 | int checkboard(void) |
| 405 | { |
| 406 | struct cpu_type *cpu; |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 407 | struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 408 | u8 val; |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 409 | |
Simon Glass | a8b5739 | 2012-12-13 20:48:48 +0000 | [diff] [blame] | 410 | cpu = gd->arch.cpu; |
York Sun | 7f945ca | 2016-11-16 13:30:06 -0800 | [diff] [blame] | 411 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 412 | printf("Board: %sRDB-PA, ", cpu->name); |
York Sun | 7f945ca | 2016-11-16 13:30:06 -0800 | [diff] [blame] | 413 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 414 | printf("Board: %sRDB-PB, ", cpu->name); |
Igor Opaniuk | f7c9176 | 2021-02-09 13:52:45 +0200 | [diff] [blame] | 415 | #if CONFIG_IS_ENABLED(DM_I2C) |
Biwen Li | 6a2d8d1 | 2020-05-01 20:04:13 +0800 | [diff] [blame] | 416 | struct udevice *dev; |
| 417 | int ret; |
| 418 | |
| 419 | ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2, |
| 420 | 1, &dev); |
| 421 | if (ret) { |
| 422 | printf("%s: Cannot find udev for a bus %d\n", __func__, |
| 423 | I2C_PCA9557_BUS_NUM); |
| 424 | return ret; |
| 425 | } |
| 426 | val = 0x0; /* no polarity inversion */ |
| 427 | dm_i2c_write(dev, 2, &val, 1); |
| 428 | #else |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 429 | i2c_set_bus_num(I2C_PCA9557_BUS_NUM); |
Tom Rini | be94c76 | 2021-08-18 23:12:35 -0400 | [diff] [blame] | 430 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 431 | val = 0x0; /* no polarity inversion */ |
| 432 | i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1); |
| 433 | #endif |
Biwen Li | 6a2d8d1 | 2020-05-01 20:04:13 +0800 | [diff] [blame] | 434 | #endif |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 435 | |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 436 | #ifdef CONFIG_SDCARD |
| 437 | /* switch to IFC to read info from CPLD */ |
| 438 | config_board_mux(MUX_TYPE_IFC); |
| 439 | #endif |
| 440 | |
York Sun | 7f945ca | 2016-11-16 13:30:06 -0800 | [diff] [blame] | 441 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 442 | val = (in_8(&cpld_data->pcba_ver) & 0xf); |
| 443 | printf("PCB: v%x.0\n", val); |
York Sun | 7f945ca | 2016-11-16 13:30:06 -0800 | [diff] [blame] | 444 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 445 | val = in_8(&cpld_data->cpld_ver); |
| 446 | printf("CPLD: v%x.%x, ", val >> 4, val & 0xf); |
| 447 | printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER)); |
| 448 | val = in_8(&cpld_data->rom_loc) & 0xf; |
| 449 | puts("Boot from: "); |
| 450 | switch (val) { |
| 451 | case 0xf: |
| 452 | config_board_mux(MUX_TYPE_CS0_NOR); |
| 453 | printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK)); |
| 454 | break; |
| 455 | case 0xe: |
| 456 | puts("SDHC\n"); |
| 457 | val = 0x60; /* set pca9557 pin input/output */ |
Igor Opaniuk | f7c9176 | 2021-02-09 13:52:45 +0200 | [diff] [blame] | 458 | #if CONFIG_IS_ENABLED(DM_I2C) |
Biwen Li | 6a2d8d1 | 2020-05-01 20:04:13 +0800 | [diff] [blame] | 459 | dm_i2c_write(dev, 3, &val, 1); |
| 460 | #else |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 461 | i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1); |
Biwen Li | 6a2d8d1 | 2020-05-01 20:04:13 +0800 | [diff] [blame] | 462 | #endif |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 463 | break; |
| 464 | case 0x5: |
| 465 | config_board_mux(MUX_TYPE_IFC); |
| 466 | config_board_mux(MUX_TYPE_CS0_NAND); |
| 467 | puts("NAND\n"); |
| 468 | break; |
| 469 | case 0x6: |
| 470 | config_board_mux(MUX_TYPE_IFC); |
| 471 | puts("SPI\n"); |
| 472 | break; |
| 473 | default: |
| 474 | puts("unknown\n"); |
| 475 | break; |
| 476 | } |
| 477 | #endif |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 478 | return 0; |
| 479 | } |
| 480 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 481 | #if defined(CONFIG_OF_BOARD_SETUP) |
| 482 | void fdt_del_flexcan(void *blob) |
| 483 | { |
| 484 | int nodeoff = 0; |
| 485 | |
| 486 | while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, |
Shengzhou Liu | a5b0ded | 2013-03-25 07:30:09 +0000 | [diff] [blame] | 487 | "fsl,p1010-flexcan")) >= 0) { |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 488 | fdt_del_node(blob, nodeoff); |
| 489 | } |
| 490 | } |
| 491 | |
| 492 | void fdt_del_spi_flash(void *blob) |
| 493 | { |
| 494 | int nodeoff = 0; |
| 495 | |
| 496 | while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, |
| 497 | "spansion,s25sl12801")) >= 0) { |
| 498 | fdt_del_node(blob, nodeoff); |
| 499 | } |
| 500 | } |
| 501 | |
| 502 | void fdt_del_spi_slic(void *blob) |
| 503 | { |
| 504 | int nodeoff = 0; |
| 505 | |
| 506 | while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, |
| 507 | "zarlink,le88266")) >= 0) { |
| 508 | fdt_del_node(blob, nodeoff); |
| 509 | } |
| 510 | } |
| 511 | |
| 512 | void fdt_del_tdm(void *blob) |
| 513 | { |
| 514 | int nodeoff = 0; |
| 515 | |
| 516 | while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, |
| 517 | "fsl,starlite-tdm")) >= 0) { |
| 518 | fdt_del_node(blob, nodeoff); |
| 519 | } |
| 520 | } |
| 521 | |
Shengzhou Liu | ceb705c | 2012-04-25 23:43:24 +0000 | [diff] [blame] | 522 | void fdt_del_sdhc(void *blob) |
| 523 | { |
| 524 | int nodeoff = 0; |
| 525 | |
| 526 | while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, |
| 527 | "fsl,esdhc")) >= 0) { |
| 528 | fdt_del_node(blob, nodeoff); |
| 529 | } |
| 530 | } |
| 531 | |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 532 | void fdt_del_ifc(void *blob) |
| 533 | { |
| 534 | int nodeoff = 0; |
| 535 | |
| 536 | while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, |
| 537 | "fsl,ifc")) >= 0) { |
| 538 | fdt_del_node(blob, nodeoff); |
| 539 | } |
| 540 | } |
| 541 | |
Shengzhou Liu | ceb705c | 2012-04-25 23:43:24 +0000 | [diff] [blame] | 542 | void fdt_disable_uart1(void *blob) |
| 543 | { |
| 544 | int nodeoff; |
| 545 | |
| 546 | nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550", |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 547 | CFG_SYS_NS16550_COM2); |
Shengzhou Liu | ceb705c | 2012-04-25 23:43:24 +0000 | [diff] [blame] | 548 | |
| 549 | if (nodeoff > 0) { |
| 550 | fdt_status_disabled(blob, nodeoff); |
| 551 | } else { |
| 552 | printf("WARNING unable to set status for fsl,ns16550 " |
| 553 | "uart1: %s\n", fdt_strerror(nodeoff)); |
| 554 | } |
| 555 | } |
| 556 | |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 557 | int ft_board_setup(void *blob, struct bd_info *bd) |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 558 | { |
| 559 | phys_addr_t base; |
| 560 | phys_size_t size; |
| 561 | struct cpu_type *cpu; |
| 562 | |
Simon Glass | a8b5739 | 2012-12-13 20:48:48 +0000 | [diff] [blame] | 563 | cpu = gd->arch.cpu; |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 564 | |
| 565 | ft_cpu_setup(blob, bd); |
| 566 | |
Simon Glass | da1a134 | 2017-08-03 12:22:15 -0600 | [diff] [blame] | 567 | base = env_get_bootm_low(); |
| 568 | size = env_get_bootm_size(); |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 569 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 570 | fdt_fixup_memory(blob, (u64)base, (u64)size); |
| 571 | |
Ramneek Mehresh | 59c48b4 | 2011-11-08 10:21:28 +0530 | [diff] [blame] | 572 | #if defined(CONFIG_HAS_FSL_DR_USB) |
Sriram Dash | 9fd465c | 2016-09-16 17:12:15 +0530 | [diff] [blame] | 573 | fsl_fdt_fixup_dr_usb(blob, bd); |
Ramneek Mehresh | 59c48b4 | 2011-11-08 10:21:28 +0530 | [diff] [blame] | 574 | #endif |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 575 | |
| 576 | /* P1014 and it's derivatives don't support CAN and eTSEC3 */ |
York Sun | 8cb6548 | 2012-07-06 17:10:33 -0500 | [diff] [blame] | 577 | if (cpu->soc_ver == SVR_P1014) { |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 578 | fdt_del_flexcan(blob); |
| 579 | fdt_del_node_and_alias(blob, "ethernet2"); |
| 580 | } |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 581 | |
| 582 | /* Delete IFC node as IFC pins are multiplexing with SDHC */ |
| 583 | if (sd_ifc_mux != MUX_TYPE_IFC) |
| 584 | fdt_del_ifc(blob); |
| 585 | else |
| 586 | fdt_del_sdhc(blob); |
| 587 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 588 | if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 589 | fdt_del_tdm(blob); |
| 590 | fdt_del_spi_slic(blob); |
Shengzhou Liu | ceb705c | 2012-04-25 23:43:24 +0000 | [diff] [blame] | 591 | } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 592 | fdt_del_flexcan(blob); |
| 593 | fdt_del_spi_flash(blob); |
Shengzhou Liu | ceb705c | 2012-04-25 23:43:24 +0000 | [diff] [blame] | 594 | fdt_disable_uart1(blob); |
| 595 | } else { |
| 596 | /* |
| 597 | * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm" |
| 598 | * explicitly, defaultly spi_cs_sel to spi-flash instead of |
| 599 | * to tdm/slic. |
| 600 | */ |
| 601 | fdt_del_tdm(blob); |
| 602 | fdt_del_flexcan(blob); |
| 603 | fdt_disable_uart1(blob); |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 604 | } |
Simon Glass | 2aec3cc | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 605 | |
| 606 | return 0; |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 607 | } |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 608 | #endif |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 609 | |
| 610 | #ifdef CONFIG_SDCARD |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 611 | int board_mmc_init(struct bd_info *bis) |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 612 | { |
| 613 | config_board_mux(MUX_TYPE_SDHC); |
| 614 | return -1; |
| 615 | } |
| 616 | #else |
| 617 | void board_reset(void) |
| 618 | { |
| 619 | /* mux to IFC to enable CPLD for reset */ |
| 620 | if (sd_ifc_mux != MUX_TYPE_IFC) |
| 621 | config_board_mux(MUX_TYPE_IFC); |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 622 | } |
| 623 | #endif |
| 624 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 625 | int misc_init_r(void) |
| 626 | { |
Tom Rini | d5c3bf2 | 2022-10-28 20:27:12 -0400 | [diff] [blame] | 627 | ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 628 | |
| 629 | if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { |
| 630 | clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM | |
| 631 | MPC85xx_PMUXCR_CAN1_UART | |
| 632 | MPC85xx_PMUXCR_CAN2_TDM | |
| 633 | MPC85xx_PMUXCR_CAN2_UART); |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 634 | config_board_mux(MUX_TYPE_CAN); |
Shengzhou Liu | ceb705c | 2012-04-25 23:43:24 +0000 | [diff] [blame] | 635 | } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 636 | clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART | |
| 637 | MPC85xx_PMUXCR_CAN1_UART); |
| 638 | setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM | |
| 639 | MPC85xx_PMUXCR_CAN1_TDM); |
| 640 | clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO); |
| 641 | setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM); |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 642 | config_board_mux(MUX_TYPE_TDM); |
Shengzhou Liu | ceb705c | 2012-04-25 23:43:24 +0000 | [diff] [blame] | 643 | } else { |
| 644 | /* defaultly spi_cs_sel to flash */ |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 645 | config_board_mux(MUX_TYPE_SPIFLASH); |
Shengzhou Liu | ceb705c | 2012-04-25 23:43:24 +0000 | [diff] [blame] | 646 | } |
| 647 | |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 648 | if (hwconfig("esdhc")) |
| 649 | config_board_mux(MUX_TYPE_SDHC); |
| 650 | else if (hwconfig("ifc")) |
| 651 | config_board_mux(MUX_TYPE_IFC); |
| 652 | |
York Sun | 7f945ca | 2016-11-16 13:30:06 -0800 | [diff] [blame] | 653 | #ifdef CONFIG_TARGET_P1010RDB_PB |
Shengzhou Liu | f0af438 | 2013-09-13 14:46:03 +0800 | [diff] [blame] | 654 | setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); |
| 655 | #endif |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 656 | return 0; |
| 657 | } |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 658 | |
Tom Rini | 9774e32 | 2018-01-03 09:13:04 -0500 | [diff] [blame] | 659 | #ifndef CONFIG_SPL_BUILD |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 660 | static int pin_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc, |
| 661 | char *const argv[]) |
Shengzhou Liu | 36446ef | 2013-09-13 14:46:02 +0800 | [diff] [blame] | 662 | { |
| 663 | if (argc < 2) |
| 664 | return CMD_RET_USAGE; |
| 665 | if (strcmp(argv[1], "ifc") == 0) |
| 666 | config_board_mux(MUX_TYPE_IFC); |
| 667 | else if (strcmp(argv[1], "sdhc") == 0) |
| 668 | config_board_mux(MUX_TYPE_SDHC); |
| 669 | else |
| 670 | return CMD_RET_USAGE; |
| 671 | return 0; |
| 672 | } |
| 673 | |
| 674 | U_BOOT_CMD( |
| 675 | mux, 2, 0, pin_mux_cmd, |
| 676 | "configure multiplexing pin for IFC/SDHC bus in runtime", |
| 677 | "bus_type (e.g. mux sdhc)" |
| 678 | ); |
Tom Rini | 9774e32 | 2018-01-03 09:13:04 -0500 | [diff] [blame] | 679 | #endif |