Masahiro Yamada | c429cbf | 2019-06-18 12:25:51 +0900 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Liviu Dudau | 8d1fdc3 | 2015-10-19 11:08:32 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) ARM Ltd 2015 |
| 4 | * |
| 5 | * Author: Liviu Dudau <Liviu.Dudau@arm.com> |
Liviu Dudau | 8d1fdc3 | 2015-10-19 11:08:32 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 8 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 9 | #include <log.h> |
Liviu Dudau | 8d1fdc3 | 2015-10-19 11:08:32 +0100 | [diff] [blame] | 10 | #include <asm/io.h> |
| 11 | #include <linux/bitops.h> |
| 12 | #include <pci_ids.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 13 | #include <linux/delay.h> |
Liviu Dudau | 8d1fdc3 | 2015-10-19 11:08:32 +0100 | [diff] [blame] | 14 | #include "pcie.h" |
| 15 | |
| 16 | /* XpressRICH3 support */ |
| 17 | #define XR3_CONFIG_BASE 0x7ff30000 |
| 18 | #define XR3_RESET_BASE 0x7ff20000 |
| 19 | |
| 20 | #define XR3_PCI_ECAM_START 0x40000000 |
| 21 | #define XR3_PCI_ECAM_SIZE 28 /* as power of 2 = 0x10000000 */ |
| 22 | #define XR3_PCI_IOSPACE_START 0x5f800000 |
| 23 | #define XR3_PCI_IOSPACE_SIZE 23 /* as power of 2 = 0x800000 */ |
| 24 | #define XR3_PCI_MEMSPACE_START 0x50000000 |
| 25 | #define XR3_PCI_MEMSPACE_SIZE 27 /* as power of 2 = 0x8000000 */ |
| 26 | #define XR3_PCI_MEMSPACE64_START 0x4000000000 |
| 27 | #define XR3_PCI_MEMSPACE64_SIZE 33 /* as power of 2 = 0x200000000 */ |
| 28 | |
| 29 | #define JUNO_V2M_MSI_START 0x2c1c0000 |
| 30 | #define JUNO_V2M_MSI_SIZE 12 /* as power of 2 = 4096 */ |
| 31 | |
| 32 | #define XR3PCI_BASIC_STATUS 0x18 |
| 33 | #define XR3PCI_BS_GEN_MASK (0xf << 8) |
| 34 | #define XR3PCI_BS_LINK_MASK 0xff |
| 35 | |
| 36 | #define XR3PCI_VIRTCHAN_CREDITS 0x90 |
| 37 | #define XR3PCI_BRIDGE_PCI_IDS 0x9c |
| 38 | #define XR3PCI_PEX_SPC2 0xd8 |
| 39 | |
| 40 | #define XR3PCI_ATR_PCIE_WIN0 0x600 |
| 41 | #define XR3PCI_ATR_PCIE_WIN1 0x700 |
| 42 | #define XR3PCI_ATR_AXI4_SLV0 0x800 |
| 43 | |
| 44 | #define XR3PCI_ATR_TABLE_SIZE 0x20 |
| 45 | #define XR3PCI_ATR_SRC_ADDR_LOW 0x0 |
| 46 | #define XR3PCI_ATR_SRC_ADDR_HIGH 0x4 |
| 47 | #define XR3PCI_ATR_TRSL_ADDR_LOW 0x8 |
| 48 | #define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc |
| 49 | #define XR3PCI_ATR_TRSL_PARAM 0x10 |
| 50 | |
| 51 | /* IDs used in the XR3PCI_ATR_TRSL_PARAM */ |
| 52 | #define XR3PCI_ATR_TRSLID_AXIDEVICE (0x420004) |
| 53 | #define XR3PCI_ATR_TRSLID_AXIMEMORY (0x4e0004) /* Write-through, read/write allocate */ |
| 54 | #define XR3PCI_ATR_TRSLID_PCIE_CONF (0x000001) |
| 55 | #define XR3PCI_ATR_TRSLID_PCIE_IO (0x020000) |
| 56 | #define XR3PCI_ATR_TRSLID_PCIE_MEMORY (0x000000) |
| 57 | |
Liviu Dudau | 8d1fdc3 | 2015-10-19 11:08:32 +0100 | [diff] [blame] | 58 | #define JUNO_RESET_CTRL 0x1004 |
| 59 | #define JUNO_RESET_CTRL_PHY BIT(0) |
| 60 | #define JUNO_RESET_CTRL_RC BIT(1) |
| 61 | |
| 62 | #define JUNO_RESET_STATUS 0x1008 |
| 63 | #define JUNO_RESET_STATUS_PLL BIT(0) |
| 64 | #define JUNO_RESET_STATUS_PHY BIT(1) |
| 65 | #define JUNO_RESET_STATUS_RC BIT(2) |
| 66 | #define JUNO_RESET_STATUS_MASK (JUNO_RESET_STATUS_PLL | \ |
| 67 | JUNO_RESET_STATUS_PHY | \ |
| 68 | JUNO_RESET_STATUS_RC) |
| 69 | |
Andre Przywara | 95486fb | 2020-06-11 12:03:20 +0100 | [diff] [blame] | 70 | static void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr, |
| 71 | unsigned long trsl_addr, int window_size, |
| 72 | int trsl_param) |
Liviu Dudau | 8d1fdc3 | 2015-10-19 11:08:32 +0100 | [diff] [blame] | 73 | { |
| 74 | /* X3PCI_ATR_SRC_ADDR_LOW: |
| 75 | - bit 0: enable entry, |
| 76 | - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1) |
| 77 | - bits 7-11: reserved |
| 78 | - bits 12-31: start of source address |
| 79 | */ |
| 80 | writel((u32)(src_addr & 0xfffff000) | (window_size - 1) << 1 | 1, |
| 81 | base + XR3PCI_ATR_SRC_ADDR_LOW); |
| 82 | writel((u32)(src_addr >> 32), base + XR3PCI_ATR_SRC_ADDR_HIGH); |
| 83 | writel((u32)(trsl_addr & 0xfffff000), base + XR3PCI_ATR_TRSL_ADDR_LOW); |
| 84 | writel((u32)(trsl_addr >> 32), base + XR3PCI_ATR_TRSL_ADDR_HIGH); |
| 85 | writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM); |
| 86 | |
Andre Przywara | 7515464 | 2015-11-13 11:25:46 +0000 | [diff] [blame] | 87 | debug("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n", |
Liviu Dudau | 8d1fdc3 | 2015-10-19 11:08:32 +0100 | [diff] [blame] | 88 | src_addr, (trsl_param & 0x400000) ? "<-" : "->", trsl_addr, |
| 89 | ((u64)1) << window_size, trsl_param); |
| 90 | } |
| 91 | |
Andre Przywara | 95486fb | 2020-06-11 12:03:20 +0100 | [diff] [blame] | 92 | static void xr3pci_setup_atr(void) |
Liviu Dudau | 8d1fdc3 | 2015-10-19 11:08:32 +0100 | [diff] [blame] | 93 | { |
| 94 | /* setup PCIe to CPU address translation tables */ |
| 95 | unsigned long base = XR3_CONFIG_BASE + XR3PCI_ATR_PCIE_WIN0; |
| 96 | |
| 97 | /* forward all writes from PCIe to GIC V2M (used for MSI) */ |
| 98 | xr3pci_set_atr_entry(base, JUNO_V2M_MSI_START, JUNO_V2M_MSI_START, |
| 99 | JUNO_V2M_MSI_SIZE, XR3PCI_ATR_TRSLID_AXIDEVICE); |
| 100 | |
| 101 | base += XR3PCI_ATR_TABLE_SIZE; |
| 102 | |
| 103 | /* PCIe devices can write anywhere in memory */ |
| 104 | xr3pci_set_atr_entry(base, PHYS_SDRAM_1, PHYS_SDRAM_1, |
| 105 | 31 /* grant access to all RAM under 4GB */, |
| 106 | XR3PCI_ATR_TRSLID_AXIMEMORY); |
| 107 | base += XR3PCI_ATR_TABLE_SIZE; |
| 108 | xr3pci_set_atr_entry(base, PHYS_SDRAM_2, PHYS_SDRAM_2, |
| 109 | XR3_PCI_MEMSPACE64_SIZE, |
| 110 | XR3PCI_ATR_TRSLID_AXIMEMORY); |
| 111 | |
Liviu Dudau | 8d1fdc3 | 2015-10-19 11:08:32 +0100 | [diff] [blame] | 112 | /* setup CPU to PCIe address translation table */ |
| 113 | base = XR3_CONFIG_BASE + XR3PCI_ATR_AXI4_SLV0; |
| 114 | |
| 115 | /* setup ECAM space to bus configuration interface */ |
| 116 | xr3pci_set_atr_entry(base, XR3_PCI_ECAM_START, 0, XR3_PCI_ECAM_SIZE, |
| 117 | XR3PCI_ATR_TRSLID_PCIE_CONF); |
| 118 | |
| 119 | base += XR3PCI_ATR_TABLE_SIZE; |
| 120 | |
| 121 | /* setup IO space translation */ |
Liviu Dudau | 313ec09 | 2016-11-22 11:19:18 +0000 | [diff] [blame] | 122 | xr3pci_set_atr_entry(base, XR3_PCI_IOSPACE_START, 0, |
Liviu Dudau | 8d1fdc3 | 2015-10-19 11:08:32 +0100 | [diff] [blame] | 123 | XR3_PCI_IOSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_IO); |
| 124 | |
| 125 | base += XR3PCI_ATR_TABLE_SIZE; |
| 126 | |
| 127 | /* setup 32bit MEM space translation */ |
| 128 | xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE_START, XR3_PCI_MEMSPACE_START, |
| 129 | XR3_PCI_MEMSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY); |
| 130 | |
| 131 | base += XR3PCI_ATR_TABLE_SIZE; |
| 132 | |
| 133 | /* setup 64bit MEM space translation */ |
| 134 | xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE64_START, XR3_PCI_MEMSPACE64_START, |
| 135 | XR3_PCI_MEMSPACE64_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY); |
| 136 | } |
| 137 | |
Andre Przywara | 95486fb | 2020-06-11 12:03:20 +0100 | [diff] [blame] | 138 | static void xr3pci_init(void) |
Liviu Dudau | 8d1fdc3 | 2015-10-19 11:08:32 +0100 | [diff] [blame] | 139 | { |
| 140 | u32 val; |
| 141 | int timeout = 200; |
| 142 | |
| 143 | /* Initialise the XpressRICH3 PCIe host bridge */ |
| 144 | |
| 145 | /* add credits */ |
| 146 | writel(0x00f0b818, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS); |
| 147 | writel(0x1, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS + 4); |
| 148 | /* allow ECRC */ |
| 149 | writel(0x6006, XR3_CONFIG_BASE + XR3PCI_PEX_SPC2); |
| 150 | /* setup the correct class code for the host bridge */ |
Pali Rohár | 25781e2 | 2022-02-18 13:18:40 +0100 | [diff] [blame] | 151 | writel(PCI_CLASS_BRIDGE_PCI_NORMAL << 8, XR3_CONFIG_BASE + XR3PCI_BRIDGE_PCI_IDS); |
Liviu Dudau | 8d1fdc3 | 2015-10-19 11:08:32 +0100 | [diff] [blame] | 152 | |
| 153 | /* reset phy and root complex */ |
| 154 | writel(JUNO_RESET_CTRL_PHY | JUNO_RESET_CTRL_RC, |
| 155 | XR3_RESET_BASE + JUNO_RESET_CTRL); |
| 156 | |
| 157 | do { |
| 158 | mdelay(1); |
| 159 | val = readl(XR3_RESET_BASE + JUNO_RESET_STATUS); |
| 160 | } while (--timeout && |
| 161 | (val & JUNO_RESET_STATUS_MASK) != JUNO_RESET_STATUS_MASK); |
| 162 | |
| 163 | if (!timeout) { |
| 164 | printf("PCI XR3 Root complex reset timed out\n"); |
| 165 | return; |
| 166 | } |
| 167 | |
| 168 | /* Wait for the link to train */ |
| 169 | mdelay(20); |
| 170 | timeout = 20; |
| 171 | |
| 172 | do { |
| 173 | mdelay(1); |
| 174 | val = readl(XR3_CONFIG_BASE + XR3PCI_BASIC_STATUS); |
| 175 | } while (--timeout && !(val & XR3PCI_BS_LINK_MASK)); |
| 176 | |
| 177 | if (!(val & XR3PCI_BS_LINK_MASK)) { |
| 178 | printf("Failed to negotiate a link!\n"); |
| 179 | return; |
| 180 | } |
| 181 | |
| 182 | printf("PCIe XR3 Host Bridge enabled: x%d link (Gen %d)\n", |
| 183 | val & XR3PCI_BS_LINK_MASK, (val & XR3PCI_BS_GEN_MASK) >> 8); |
| 184 | |
| 185 | xr3pci_setup_atr(); |
| 186 | } |
| 187 | |
| 188 | void vexpress64_pcie_init(void) |
| 189 | { |
Andre Przywara | 95486fb | 2020-06-11 12:03:20 +0100 | [diff] [blame] | 190 | /* Initialise and configure the PCIe host bridge. */ |
Liviu Dudau | 8d1fdc3 | 2015-10-19 11:08:32 +0100 | [diff] [blame] | 191 | xr3pci_init(); |
Andre Przywara | 95486fb | 2020-06-11 12:03:20 +0100 | [diff] [blame] | 192 | |
| 193 | /* Register the now ECAM complaint PCIe host controller with U-Boot. */ |
| 194 | pci_init(); |
Liviu Dudau | 8d1fdc3 | 2015-10-19 11:08:32 +0100 | [diff] [blame] | 195 | } |