blob: c1190667cef6c5e29f7e7a775de74a96d62120da [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Prabhakar Kushwaha934e6ed2011-01-20 16:34:41 +05302/*
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
Prabhakar Kushwaha934e6ed2011-01-20 16:34:41 +05305 */
6
7#include <config.h>
Simon Glass0f2af882020-05-10 11:40:05 -06008#include <log.h>
Prabhakar Kushwaha934e6ed2011-01-20 16:34:41 +05309#include <asm/io.h>
10#include <asm/immap_85xx.h>
11#include <asm/fsl_serdes.h>
12
13#define SRDS1_MAX_LANES 4
14#define SRDS2_MAX_LANES 2
15
16static u32 serdes1_prtcl_map, serdes2_prtcl_map;
17
18static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
19 [0x00] = {NONE, NONE, NONE, NONE},
20 [0x01] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3},
21 [0x02] = {PCIE1, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3},
22 [0x03] = {NONE, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3},
23};
24
25static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
26 [0x00] = {NONE, NONE},
27 [0x01] = {SATA1, SATA2},
28 [0x02] = {SATA1, SATA2},
29 [0x03] = {PCIE1, PCIE2},
30};
31
Prabhakar Kushwaha934e6ed2011-01-20 16:34:41 +053032int is_serdes_configured(enum srds_prtcl device)
33{
Hou Zhiqiangb435ae92016-08-02 19:03:22 +080034 int ret;
35
36 if (!(serdes1_prtcl_map & (1 << NONE)))
37 fsl_serdes_init();
38
39 ret = (1 << device) & serdes1_prtcl_map;
Prabhakar Kushwaha934e6ed2011-01-20 16:34:41 +053040
41 if (ret)
42 return ret;
43
Hou Zhiqiangb435ae92016-08-02 19:03:22 +080044 if (!(serdes2_prtcl_map & (1 << NONE)))
45 fsl_serdes_init();
46
Prabhakar Kushwaha934e6ed2011-01-20 16:34:41 +053047 return (1 << device) & serdes2_prtcl_map;
48}
49
50void fsl_serdes_init(void)
51{
Tom Rinid5c3bf22022-10-28 20:27:12 -040052 ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
Prabhakar Kushwaha934e6ed2011-01-20 16:34:41 +053053 u32 pordevsr = in_be32(&gur->pordevsr);
54 u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
55 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
56 int lane;
57
Hou Zhiqiangb435ae92016-08-02 19:03:22 +080058 if (serdes1_prtcl_map & (1 << NONE) &&
59 serdes2_prtcl_map & (1 << NONE))
60 return;
61
Prabhakar Kushwaha934e6ed2011-01-20 16:34:41 +053062 debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
63
Axel Linab95b092013-05-26 15:00:30 +080064 if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
Prabhakar Kushwaha934e6ed2011-01-20 16:34:41 +053065 printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
66 return;
67 }
68 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
69 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
70 serdes1_prtcl_map |= (1 << lane_prtcl);
71 }
72
Hou Zhiqiangb435ae92016-08-02 19:03:22 +080073 /* Set the first bit to indicate serdes has been initialized */
74 serdes1_prtcl_map |= (1 << NONE);
75
Axel Linab95b092013-05-26 15:00:30 +080076 if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
Prabhakar Kushwaha934e6ed2011-01-20 16:34:41 +053077 printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
78 return;
79 }
80
81 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
82 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
83 serdes2_prtcl_map |= (1 << lane_prtcl);
84 }
Hou Zhiqiangb435ae92016-08-02 19:03:22 +080085
86 /* Set the first bit to indicate serdes has been initialized */
87 serdes2_prtcl_map |= (1 << NONE);
Prabhakar Kushwaha934e6ed2011-01-20 16:34:41 +053088}