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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenke65527f2004-02-12 00:47:09 +00002/*
3 * (C) Copyright 2003
4 * Josef Baumgartner <josef.baumgartner@telex.de>
5 *
Heiko Schocherac1956e2006-04-20 08:42:42 +02006 * MCF5282 additionals
7 * (C) Copyright 2005
8 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
9 *
Matthew Fettke761e2e92008-02-04 15:38:20 -060010 * MCF5275 additions
11 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
12 *
Alison Wang95bed1f2012-03-26 21:49:04 +000013 * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
wdenke65527f2004-02-12 00:47:09 +000014 */
15
Simon Glass97589732020-05-10 11:40:02 -060016#include <init.h>
Simon Glass274e0b02020-05-10 11:39:56 -060017#include <net.h>
Simon Glassf5c208d2019-11-14 12:57:20 -070018#include <vsprintf.h>
wdenke65527f2004-02-12 00:47:09 +000019#include <command.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060020#include <asm/global_data.h>
TsiChungLiew8cd73be2007-08-15 19:21:21 -050021#include <asm/immap.h>
Alison Wang95bed1f2012-03-26 21:49:04 +000022#include <asm/io.h>
Ben Warren2f2b6b62008-08-31 22:22:04 -070023#include <netdev.h>
Simon Glassdbd79542020-05-10 11:40:11 -060024#include <linux/delay.h>
Richard Retanubun5ffa65b2009-10-26 14:19:17 -040025#include "cpu.h"
wdenke65527f2004-02-12 00:47:09 +000026
TsiChung Liewb354aef2009-06-12 11:29:00 +000027DECLARE_GLOBAL_DATA_PTR;
28
29#ifdef CONFIG_M5208
Simon Glassed38aef2020-05-10 11:40:03 -060030int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
TsiChung Liewb354aef2009-06-12 11:29:00 +000031{
Alison Wang95bed1f2012-03-26 21:49:04 +000032 rcm_t *rcm = (rcm_t *)(MMAP_RCM);
TsiChung Liewb354aef2009-06-12 11:29:00 +000033
34 udelay(1000);
35
Alison Wang95bed1f2012-03-26 21:49:04 +000036 out_8(&rcm->rcr, RCM_RCR_SOFTRST);
TsiChung Liewb354aef2009-06-12 11:29:00 +000037
38 /* we don't return! */
39 return 0;
40};
41
Angelo Dureghello3146b4d2017-08-20 00:01:55 +020042#if defined(CONFIG_DISPLAY_CPUINFO)
43int print_cpuinfo(void)
TsiChung Liewb354aef2009-06-12 11:29:00 +000044{
45 char buf1[32], buf2[32];
46
47 printf("CPU: Freescale Coldfire MCF5208\n"
48 " CPU CLK %s MHz BUS CLK %s MHz\n",
49 strmhz(buf1, gd->cpu_clk),
50 strmhz(buf2, gd->bus_clk));
51 return 0;
52};
Angelo Dureghello3146b4d2017-08-20 00:01:55 +020053#endif /* CONFIG_DISPLAY_CPUINFO */
Angelo Dureghello4a7039f2023-06-24 23:22:23 +020054#endif /* #ifdef CONFIG_M5208 */
TsiChung Liewb354aef2009-06-12 11:29:00 +000055
Zachary P. Landau0bba8622006-01-26 17:35:56 -050056#ifdef CONFIG_M5271
Angelo Dureghello3146b4d2017-08-20 00:01:55 +020057#if defined(CONFIG_DISPLAY_CPUINFO)
Bartlomiej Siekaad870262007-01-23 13:25:22 +010058/*
59 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
60 * determine which one we are running on, based on the Chip Identification
61 * Register (CIR).
62 */
Angelo Dureghello3146b4d2017-08-20 00:01:55 +020063int print_cpuinfo(void)
Zachary P. Landau0bba8622006-01-26 17:35:56 -050064{
Marian Balakowiczecb6d0b2006-05-09 11:45:31 +020065 char buf[32];
Bartlomiej Siekaad870262007-01-23 13:25:22 +010066 unsigned short cir; /* Chip Identification Register */
67 unsigned short pin; /* Part identification number */
68 unsigned char prn; /* Part revision number */
69 char *cpu_model;
70
71 cir = mbar_readShort(MCF_CCM_CIR);
72 pin = cir >> MCF_CCM_CIR_PIN_LEN;
73 prn = cir & MCF_CCM_CIR_PRN_MASK;
74
75 switch (pin) {
76 case MCF_CCM_CIR_PIN_MCF5270:
77 cpu_model = "5270";
78 break;
79 case MCF_CCM_CIR_PIN_MCF5271:
80 cpu_model = "5271";
81 break;
82 default:
83 cpu_model = NULL;
84 break;
85 }
86
87 if (cpu_model)
88 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
Tom Rini6a5dccc2022-11-16 13:10:41 -050089 cpu_model, prn, strmhz(buf, CFG_SYS_CLK));
Bartlomiej Siekaad870262007-01-23 13:25:22 +010090 else
91 printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
TsiChungLiew8cd73be2007-08-15 19:21:21 -050092 " (PIN: 0x%x) rev. %hu, at %s MHz\n",
Tom Rini6a5dccc2022-11-16 13:10:41 -050093 pin, prn, strmhz(buf, CFG_SYS_CLK));
Marian Balakowiczecb6d0b2006-05-09 11:45:31 +020094
Zachary P. Landau0bba8622006-01-26 17:35:56 -050095 return 0;
96}
Angelo Dureghello3146b4d2017-08-20 00:01:55 +020097#endif /* CONFIG_DISPLAY_CPUINFO */
Zachary P. Landau0bba8622006-01-26 17:35:56 -050098
Simon Glassed38aef2020-05-10 11:40:03 -060099int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
TsiChungLiew8cd73be2007-08-15 19:21:21 -0500100{
Richard Retanubun5ffa65b2009-10-26 14:19:17 -0400101 /* Call the board specific reset actions first. */
102 if(board_reset) {
103 board_reset();
104 }
105
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500106 mbar_writeByte(MCF_RCM_RCR,
TsiChungLiew8cd73be2007-08-15 19:21:21 -0500107 MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500108 return 0;
109};
110
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500111#endif
wdenke65527f2004-02-12 00:47:09 +0000112
113#ifdef CONFIG_M5272
Simon Glassed38aef2020-05-10 11:40:03 -0600114int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
TsiChungLiew8cd73be2007-08-15 19:21:21 -0500115{
Alison Wang95bed1f2012-03-26 21:49:04 +0000116 wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
wdenke65527f2004-02-12 00:47:09 +0000117
Alison Wang95bed1f2012-03-26 21:49:04 +0000118 out_be16(&wdp->wdog_wrrr, 0);
TsiChungLiew8cd73be2007-08-15 19:21:21 -0500119 udelay(1000);
wdenke65527f2004-02-12 00:47:09 +0000120
121 /* enable watchdog, set timeout to 0 and wait */
Alison Wang95bed1f2012-03-26 21:49:04 +0000122 out_be16(&wdp->wdog_wrrr, 1);
TsiChungLiew8cd73be2007-08-15 19:21:21 -0500123 while (1) ;
wdenke65527f2004-02-12 00:47:09 +0000124
125 /* we don't return! */
126 return 0;
127};
128
Angelo Dureghello3146b4d2017-08-20 00:01:55 +0200129#if defined(CONFIG_DISPLAY_CPUINFO)
130int print_cpuinfo(void)
TsiChungLiew8cd73be2007-08-15 19:21:21 -0500131{
Alison Wang95bed1f2012-03-26 21:49:04 +0000132 sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
wdenke65527f2004-02-12 00:47:09 +0000133 uchar msk;
TsiChungLiew8cd73be2007-08-15 19:21:21 -0500134 char *suf;
wdenke65527f2004-02-12 00:47:09 +0000135
TsiChungLiew8cd73be2007-08-15 19:21:21 -0500136 puts("CPU: ");
Alison Wang95bed1f2012-03-26 21:49:04 +0000137 msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf;
wdenke65527f2004-02-12 00:47:09 +0000138 switch (msk) {
TsiChungLiew8cd73be2007-08-15 19:21:21 -0500139 case 0x2:
140 suf = "1K75N";
141 break;
142 case 0x4:
143 suf = "3K75N";
144 break;
145 default:
146 suf = NULL;
147 printf("Freescale MCF5272 (Mask:%01x)\n", msk);
148 break;
149 }
wdenke65527f2004-02-12 00:47:09 +0000150
151 if (suf)
TsiChungLiew8cd73be2007-08-15 19:21:21 -0500152 printf("Freescale MCF5272 %s\n", suf);
wdenke65527f2004-02-12 00:47:09 +0000153 return 0;
154};
Angelo Dureghello3146b4d2017-08-20 00:01:55 +0200155#endif /* CONFIG_DISPLAY_CPUINFO */
wdenke65527f2004-02-12 00:47:09 +0000156
TsiChungLiew8cd73be2007-08-15 19:21:21 -0500157#endif /* #ifdef CONFIG_M5272 */
wdenke65527f2004-02-12 00:47:09 +0000158
Matthew Fettke761e2e92008-02-04 15:38:20 -0600159#ifdef CONFIG_M5275
Simon Glassed38aef2020-05-10 11:40:03 -0600160int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
Matthew Fettke761e2e92008-02-04 15:38:20 -0600161{
Alison Wang95bed1f2012-03-26 21:49:04 +0000162 rcm_t *rcm = (rcm_t *)(MMAP_RCM);
Matthew Fettke761e2e92008-02-04 15:38:20 -0600163
164 udelay(1000);
165
Alison Wang95bed1f2012-03-26 21:49:04 +0000166 out_8(&rcm->rcr, RCM_RCR_SOFTRST);
Matthew Fettke761e2e92008-02-04 15:38:20 -0600167
168 /* we don't return! */
169 return 0;
170};
171
Angelo Dureghello3146b4d2017-08-20 00:01:55 +0200172#if defined(CONFIG_DISPLAY_CPUINFO)
173int print_cpuinfo(void)
Matthew Fettke761e2e92008-02-04 15:38:20 -0600174{
175 char buf[32];
176
177 printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
Tom Rini6a5dccc2022-11-16 13:10:41 -0500178 strmhz(buf, CFG_SYS_CLK));
Matthew Fettke761e2e92008-02-04 15:38:20 -0600179 return 0;
180};
Angelo Dureghello3146b4d2017-08-20 00:01:55 +0200181#endif /* CONFIG_DISPLAY_CPUINFO */
Matthew Fettke761e2e92008-02-04 15:38:20 -0600182
Matthew Fettke761e2e92008-02-04 15:38:20 -0600183#endif /* #ifdef CONFIG_M5275 */
184
wdenke65527f2004-02-12 00:47:09 +0000185#ifdef CONFIG_M5282
Angelo Dureghello3146b4d2017-08-20 00:01:55 +0200186#if defined(CONFIG_DISPLAY_CPUINFO)
187int print_cpuinfo(void)
wdenke65527f2004-02-12 00:47:09 +0000188{
Wolfgang Denkb4b1c462006-06-10 19:27:47 +0200189 unsigned char resetsource = MCFRESET_RSR;
Heiko Schocherac1956e2006-04-20 08:42:42 +0200190
TsiChungLiew8cd73be2007-08-15 19:21:21 -0500191 printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
192 MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
193 printf("Reset:%s%s%s%s%s%s%s\n",
194 (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
195 (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
196 (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
197 (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
198 (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
199 (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
200 (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
wdenke65527f2004-02-12 00:47:09 +0000201 return 0;
202}
Angelo Dureghello3146b4d2017-08-20 00:01:55 +0200203#endif /* CONFIG_DISPLAY_CPUINFO */
wdenke65527f2004-02-12 00:47:09 +0000204
Simon Glassed38aef2020-05-10 11:40:03 -0600205int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
Heiko Schocherac1956e2006-04-20 08:42:42 +0200206{
207 MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
wdenke65527f2004-02-12 00:47:09 +0000208 return 0;
209};
210#endif
stroese53395a22004-12-16 18:09:49 +0000211
TsiChungLiew34674692007-08-16 13:20:50 -0500212#ifdef CONFIG_M5249
Angelo Dureghello3146b4d2017-08-20 00:01:55 +0200213#if defined(CONFIG_DISPLAY_CPUINFO)
214int print_cpuinfo(void)
stroese53395a22004-12-16 18:09:49 +0000215{
216 char buf[32];
217
TsiChungLiew8cd73be2007-08-15 19:21:21 -0500218 printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
Tom Rini6a5dccc2022-11-16 13:10:41 -0500219 strmhz(buf, CFG_SYS_CLK));
stroese53395a22004-12-16 18:09:49 +0000220 return 0;
221}
Angelo Dureghello3146b4d2017-08-20 00:01:55 +0200222#endif /* CONFIG_DISPLAY_CPUINFO */
stroese53395a22004-12-16 18:09:49 +0000223
Simon Glassed38aef2020-05-10 11:40:03 -0600224int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
TsiChungLiew8cd73be2007-08-15 19:21:21 -0500225{
stroese53395a22004-12-16 18:09:49 +0000226 /* enable watchdog, set timeout to 0 and wait */
227 mbar_writeByte(MCFSIM_SYPCR, 0xc0);
TsiChungLiew8cd73be2007-08-15 19:21:21 -0500228 while (1) ;
stroese53395a22004-12-16 18:09:49 +0000229
230 /* we don't return! */
231 return 0;
232};
233#endif
TsiChungLiew34674692007-08-16 13:20:50 -0500234
235#ifdef CONFIG_M5253
Angelo Dureghello3146b4d2017-08-20 00:01:55 +0200236#if defined(CONFIG_DISPLAY_CPUINFO)
237int print_cpuinfo(void)
TsiChungLiew34674692007-08-16 13:20:50 -0500238{
239 char buf[32];
240
241 unsigned char resetsource = mbar_readLong(SIM_RSR);
242 printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
Tom Rini6a5dccc2022-11-16 13:10:41 -0500243 strmhz(buf, CFG_SYS_CLK));
TsiChungLiew34674692007-08-16 13:20:50 -0500244
245 if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
246 printf("Reset:%s%s\n",
247 (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
248 : "",
249 (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
250 "");
251 }
252 return 0;
253}
Angelo Dureghello3146b4d2017-08-20 00:01:55 +0200254#endif /* CONFIG_DISPLAY_CPUINFO */
TsiChungLiew34674692007-08-16 13:20:50 -0500255
Simon Glassed38aef2020-05-10 11:40:03 -0600256int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
TsiChungLiew34674692007-08-16 13:20:50 -0500257{
258 /* enable watchdog, set timeout to 0 and wait */
259 mbar_writeByte(SIM_SYPCR, 0xc0);
260 while (1) ;
261
262 /* we don't return! */
263 return 0;
264};
265#endif
Ben Warren90c96db2008-08-26 22:16:25 -0700266
267#if defined(CONFIG_MCFFEC)
268/* Default initializations for MCFFEC controllers. To override,
269 * create a board-specific function called:
Wolfgang Denk62fb2b42021-09-27 17:42:39 +0200270 * int board_eth_init(struct bd_info *bis)
Ben Warren90c96db2008-08-26 22:16:25 -0700271 */
272
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900273int cpu_eth_init(struct bd_info *bis)
Ben Warren90c96db2008-08-26 22:16:25 -0700274{
275 return mcffec_initialize(bis);
276}
277#endif