Jim Liu | 147c000 | 2022-09-27 16:45:15 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (c) 2022 Nuvoton Technology Corp. |
| 4 | */ |
| 5 | |
Jim Liu | 147c000 | 2022-09-27 16:45:15 +0800 | [diff] [blame] | 6 | #include <asm/io.h> |
| 7 | #include <asm/arch/gcr.h> |
| 8 | #include <asm/arch/rst.h> |
| 9 | |
| 10 | void reset_cpu(void) |
| 11 | { |
| 12 | /* Generate a watchdog0 reset */ |
| 13 | writel(WTCR_WTR | WTCR_WTRE | WTCR_WTE, WTCR0_REG); |
| 14 | |
| 15 | while (1) |
| 16 | ; |
| 17 | } |
| 18 | |
| 19 | void reset_misc(void) |
| 20 | { |
| 21 | struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA; |
| 22 | |
| 23 | clrbits_le32(&gcr->intcr2, INTCR2_WDC); |
| 24 | } |
| 25 | |
| 26 | int npcm_get_reset_status(void) |
| 27 | { |
| 28 | struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA; |
| 29 | u32 val; |
| 30 | |
| 31 | val = readl(&gcr->ressr); |
| 32 | if (!val) |
| 33 | val = readl(&gcr->intcr2); |
| 34 | |
| 35 | return val & RST_STS_MASK; |
| 36 | } |