blob: e28b4ae7ae4bcba17aeec2a640bb0f765ff5e2e2 [file] [log] [blame]
Jim Liu147c0002022-09-27 16:45:15 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2022 Nuvoton Technology Corp.
4 */
5
Jim Liu147c0002022-09-27 16:45:15 +08006#include <asm/io.h>
7#include <asm/arch/gcr.h>
8#include <asm/arch/rst.h>
9
10void reset_cpu(void)
11{
12 /* Generate a watchdog0 reset */
13 writel(WTCR_WTR | WTCR_WTRE | WTCR_WTE, WTCR0_REG);
14
15 while (1)
16 ;
17}
18
19void reset_misc(void)
20{
21 struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
22
23 clrbits_le32(&gcr->intcr2, INTCR2_WDC);
24}
25
26int npcm_get_reset_status(void)
27{
28 struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
29 u32 val;
30
31 val = readl(&gcr->ressr);
32 if (!val)
33 val = readl(&gcr->intcr2);
34
35 return val & RST_STS_MASK;
36}