blob: c04bcb6351780d077f67e7c47701e833a4656b8d [file] [log] [blame]
developer9445eda2019-11-07 19:28:40 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Configuration for MediaTek MT8518 SoC
4 *
5 * Copyright (C) 2019 MediaTek Inc.
6 * Author: Mingming Lee <mingming.lee@mediatek.com>
7 */
8
9#include <clk.h>
Simon Glassafb02152019-12-28 10:45:01 -070010#include <cpu_func.h>
developer9445eda2019-11-07 19:28:40 +080011#include <dm.h>
12#include <fdtdec.h>
Simon Glass97589732020-05-10 11:40:02 -060013#include <init.h>
developer9445eda2019-11-07 19:28:40 +080014#include <ram.h>
15#include <asm/arch/misc.h>
16#include <asm/armv8/mmu.h>
Simon Glass274e0b02020-05-10 11:39:56 -060017#include <asm/cache.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060018#include <asm/global_data.h>
developer9445eda2019-11-07 19:28:40 +080019#include <asm/sections.h>
20#include <dm/uclass.h>
21#include <dt-bindings/clock/mt8518-clk.h>
22
23DECLARE_GLOBAL_DATA_PTR;
24
25int dram_init(void)
26{
27 int ret;
28
29 ret = fdtdec_setup_memory_banksize();
30 if (ret)
31 return ret;
32
33 return fdtdec_setup_mem_size_base();
34}
35
36int dram_init_banksize(void)
37{
38 gd->bd->bi_dram[0].start = gd->ram_base;
39 gd->bd->bi_dram[0].size = gd->ram_size;
40
41 return 0;
42}
43
Harald Seiler6f14d5f2020-12-15 16:47:52 +010044void reset_cpu(void)
developer9445eda2019-11-07 19:28:40 +080045{
46 psci_system_reset();
47}
48
49int print_cpuinfo(void)
50{
51 printf("CPU: MediaTek MT8518\n");
52 return 0;
53}
54
55static struct mm_region mt8518_mem_map[] = {
56 {
57 /* DDR */
58 .virt = 0x40000000UL,
59 .phys = 0x40000000UL,
60 .size = 0x20000000UL,
61 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
62 }, {
63 .virt = 0x00000000UL,
64 .phys = 0x00000000UL,
65 .size = 0x20000000UL,
66 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
67 PTE_BLOCK_NON_SHARE |
68 PTE_BLOCK_PXN | PTE_BLOCK_UXN
69 }, {
70 0,
71 }
72};
73
74struct mm_region *mem_map = mt8518_mem_map;