| Jayesh Choudhary | e1f87a0 | 2024-06-14 18:14:38 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Keystone3 Quality of service endpoint definitions |
| 4 | * Auto generated by K3 Resource Partitioning Tool |
| 5 | * |
| 6 | * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ |
| 7 | */ |
| 8 | |
| 9 | #define SMS_WKUP_0_TIFS_VBUSP_M 0x45D00000 |
| 10 | #define SMS_WKUP_0_HSM_VBUSP_M 0x45D00400 |
| 11 | #define PULSAR_SL_MCU_0_CPU0_RMST 0x45D10000 |
| 12 | #define PULSAR_SL_MCU_0_CPU0_WMST 0x45D10400 |
| 13 | #define PULSAR_SL_MCU_0_CPU0_PMST 0x45D10800 |
| 14 | #define PULSAR_SL_MCU_0_CPU1_RMST 0x45D11000 |
| 15 | #define PULSAR_SL_MCU_0_CPU1_WMST 0x45D11400 |
| 16 | #define PULSAR_SL_MCU_0_CPU1_PMST 0x45D11800 |
| 17 | #define SA3SS_AM62_MCU_0_CTXCACH_EXT_DMA 0x45D13000 |
| 18 | #define PULSAR_SL_MAIN_0_PBDG_RMST0 0x45D78000 |
| 19 | #define PULSAR_SL_MAIN_0_PBDG_WMST0 0x45D78400 |
| 20 | #define PULSAR_SL_MAIN_0_PBDG_RMST1 0x45D78800 |
| 21 | #define PULSAR_SL_MAIN_0_PBDG_WMST1 0x45D78C00 |
| 22 | #define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D82800 |
| 23 | #define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D82C00 |
| 24 | #define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM 0x45D86000 |
| 25 | #define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM 0x45D86400 |
| 26 | #define PCIE_G3X4_128_MAIN_0_PCIE_MST_RD 0x45D98400 |
| 27 | #define PCIE_G3X4_128_MAIN_0_PCIE_MST_WR 0x45D98C00 |
| 28 | #define PCIE_G3X4_128_MAIN_1_PCIE_MST_RD 0x45D99400 |
| 29 | #define PCIE_G3X4_128_MAIN_1_PCIE_MST_WR 0x45D99C00 |
| 30 | #define USB3P0SS_16FFC_MAIN_0_MSTR0 0x45D9A000 |
| 31 | #define USB3P0SS_16FFC_MAIN_0_MSTW0 0x45D9A400 |
| 32 | #define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_RD 0x45D9AC00 |
| 33 | #define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR 0x45D9B000 |
| 34 | #define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D9B400 |
| 35 | #define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D9B800 |
| 36 | #define SA2_UL_MAIN_0_CTXCACH_EXT_DMA 0x45D9BC00 |
| 37 | #define VUSR_DUAL_MAIN_0_V0_M 0x45D9C000 |
| 38 | #define VUSR_DUAL_MAIN_0_V1_M 0x45D9C400 |
| 39 | #define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45DA0000 |
| 40 | #define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45DA0400 |
| 41 | #define PULSAR_SL_MAIN_1_CPU0_RMST 0x45DA8000 |
| 42 | #define PULSAR_SL_MAIN_1_CPU0_WMST 0x45DA8400 |
| 43 | #define PULSAR_SL_MAIN_1_CPU1_RMST 0x45DA8800 |
| 44 | #define PULSAR_SL_MAIN_1_CPU1_WMST 0x45DA8C00 |
| 45 | #define PULSAR_SL_MAIN_2_CPU0_RMST 0x45DA9000 |
| 46 | #define PULSAR_SL_MAIN_2_CPU0_WMST 0x45DA9400 |
| 47 | #define PULSAR_SL_MAIN_2_CPU1_RMST 0x45DA9800 |
| 48 | #define PULSAR_SL_MAIN_2_CPU1_WMST 0x45DA9C00 |
| 49 | #define DMPAC_TOP_MAIN_0_DATA_MST 0x45DC0000 |
| 50 | #define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45DC0C00 |
| 51 | #define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45DC1000 |
| 52 | #define VPAC_TOP_MAIN_0_DATA_MST_0 0x45DC1400 |
| 53 | #define VPAC_TOP_MAIN_0_DATA_MST_1 0x45DC1800 |
| 54 | #define VPAC_TOP_MAIN_0_LDC0_M_MST 0x45DC1C00 |
| 55 | #define K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA 0x45DC2000 |
| 56 | #define K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC 0x45DC2400 |
| 57 | #define VPAC_TOP_MAIN_1_LDC0_M_MST 0x45DC2800 |
| 58 | #define VPAC_TOP_MAIN_1_DATA_MST_0 0x45DC2C00 |
| 59 | #define VPAC_TOP_MAIN_1_DATA_MST_1 0x45DC3000 |
| 60 | #define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45DC3400 |
| 61 | #define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45DC3800 |
| 62 | #define K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_R_ASYNC 0x45DC3C00 |
| 63 | #define K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_W_ASYNC 0x45DC4000 |
| 64 | #define K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_R_ASYNC 0x45DC4400 |
| 65 | #define K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_W_ASYNC 0x45DC4800 |
| 66 | #define J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC 0x45DC5000 |
| 67 | #define J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC 0x45DC5800 |
| 68 | #define PULSAR_SL_MAIN_0_CPU0_RMST 0x45DC8000 |
| 69 | #define PULSAR_SL_MAIN_0_CPU0_WMST 0x45DC8400 |
| 70 | #define PULSAR_SL_MAIN_0_CPU1_RMST 0x45DC8800 |
| 71 | #define PULSAR_SL_MAIN_0_CPU1_WMST 0x45DC8C00 |
| 72 | #define PULSAR_SL_MAIN_1_PBDG_RMST0 0x45DCA000 |
| 73 | #define PULSAR_SL_MAIN_1_PBDG_WMST0 0x45DCA400 |
| 74 | #define PULSAR_SL_MAIN_1_PBDG_RMST1 0x45DCA800 |
| 75 | #define PULSAR_SL_MAIN_1_PBDG_WMST1 0x45DCAC00 |
| 76 | #define PULSAR_SL_MAIN_2_PBDG_RMST0 0x45DCB000 |
| 77 | #define PULSAR_SL_MAIN_2_PBDG_WMST0 0x45DCB400 |
| 78 | #define PULSAR_SL_MAIN_2_PBDG_RMST1 0x45DCB800 |
| 79 | #define PULSAR_SL_MAIN_2_PBDG_WMST1 0x45DCBC00 |