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git01.mediatek.com / filogic / uboot / 1d52512b2e81dbfae2cf11f6ef886bc22a7cd4d8 / . / arch / arm / dts / tegra30-wexler-qc750.dts
blob: 87c2a4072e196caf5e5a94203eaeb2732e3816d2 [file] [log] [blame]
Svyatoslav Ryhelb8aa0b92023-07-11 13:47:02 +0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4/* CPU Speedo ID 7, Soc Speedo ID 1, CPU Process: 4, Core Process: 0 */
5
6#include <dt-bindings/input/input.h>
7#include <dt-bindings/pmic/max77663.h>
8
9#include "tegra30.dtsi"
10
11/ {
12 model = "Wexler Tab 7t";
13 compatible = "wexler,qc750", "nvidia,tegra30";
14
15 chosen {
16 stdout-path = &uartd;
17 };
18
19 aliases {
20 i2c0 = &pwr_i2c;
21
22 mmc0 = &sdmmc4; /* eMMC */
23 mmc1 = &sdmmc1; /* uSD slot */
24
25 rtc0 = &pmic;
26 rtc1 = "/rtc@7000e000";
27
28 usb0 = &micro_usb;
29 usb1 = &usb3; /* Full size USB */
30 };
31
32 memory {
33 device_type = "memory";
34 reg = <0x80000000 0x40000000>;
35 };
36
37 host1x@50000000 {
38 dc@54200000 {
39 rgb {
40 status = "okay";
41
42 nvidia,panel = <&panel>;
43 };
44 };
45 };
46
47 pinmux@70000868 {
48 pinctrl-names = "default";
49 pinctrl-0 = <&state_default>;
50
51 state_default: pinmux {
52 /* SDMMC1 pinmux */
53 sdmmc1-clk {
54 nvidia,pins = "sdmmc1_clk_pz0";
55 nvidia,function = "sdmmc1";
56 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
57 nvidia,tristate = <TEGRA_PIN_DISABLE>;
58 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
59 };
60 sdmmc1-cmd {
61 nvidia,pins = "sdmmc1_dat3_py4",
62 "sdmmc1_dat2_py5",
63 "sdmmc1_dat1_py6",
64 "sdmmc1_dat0_py7",
65 "sdmmc1_cmd_pz1";
66 nvidia,function = "sdmmc1";
67 nvidia,pull = <TEGRA_PIN_PULL_UP>;
68 nvidia,tristate = <TEGRA_PIN_DISABLE>;
69 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
70 };
71 sdmmc1-cd {
72 nvidia,pins = "gmi_iordy_pi5";
73 nvidia,function = "rsvd1";
74 nvidia,pull = <TEGRA_PIN_PULL_UP>;
75 nvidia,tristate = <TEGRA_PIN_DISABLE>;
76 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
77 };
78
79 /* SDMMC3 pinmux */
80 sdmmc3-clk {
81 nvidia,pins = "sdmmc3_clk_pa6";
82 nvidia,function = "sdmmc3";
83 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
84 nvidia,tristate = <TEGRA_PIN_DISABLE>;
85 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
86 };
87 sdmmc3-cmd {
88 nvidia,pins = "sdmmc3_cmd_pa7",
89 "sdmmc3_dat0_pb7",
90 "sdmmc3_dat1_pb6",
91 "sdmmc3_dat2_pb5",
92 "sdmmc3_dat3_pb4",
93 "sdmmc3_dat4_pd1",
94 "sdmmc3_dat5_pd0",
95 "sdmmc3_dat6_pd3",
96 "sdmmc3_dat7_pd4";
97 nvidia,function = "sdmmc3";
98 nvidia,pull = <TEGRA_PIN_PULL_UP>;
99 nvidia,tristate = <TEGRA_PIN_DISABLE>;
100 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
101 };
102
103 /* SDMMC4 pinmux */
104 sdmmc4-clk {
105 nvidia,pins = "sdmmc4_clk_pcc4";
106 nvidia,function = "sdmmc4";
107 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
108 nvidia,tristate = <TEGRA_PIN_DISABLE>;
109 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
110 };
111 sdmmc4-cmd {
112 nvidia,pins = "sdmmc4_cmd_pt7",
113 "sdmmc4_dat0_paa0",
114 "sdmmc4_dat1_paa1",
115 "sdmmc4_dat2_paa2",
116 "sdmmc4_dat3_paa3",
117 "sdmmc4_dat4_paa4",
118 "sdmmc4_dat5_paa5",
119 "sdmmc4_dat6_paa6",
120 "sdmmc4_dat7_paa7";
121 nvidia,function = "sdmmc4";
122 nvidia,pull = <TEGRA_PIN_PULL_UP>;
123 nvidia,tristate = <TEGRA_PIN_DISABLE>;
124 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
125 };
126 sdmmc4-rst-n {
127 nvidia,pins = "sdmmc4_rst_n_pcc3";
128 nvidia,function = "rsvd2";
129 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
130 nvidia,tristate = <TEGRA_PIN_DISABLE>;
131 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
132 };
133 cam-mclk {
134 nvidia,pins = "cam_mclk_pcc0";
135 nvidia,function = "vi_alt3";
136 nvidia,pull = <TEGRA_PIN_PULL_UP>;
137 nvidia,tristate = <TEGRA_PIN_DISABLE>;
138 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
139 };
140 drive-sdmmc4 {
141 nvidia,pins = "drive_gma",
142 "drive_gmb",
143 "drive_gmc",
144 "drive_gmd";
145 nvidia,pull-down-strength = <9>;
146 nvidia,pull-up-strength = <9>;
147 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
148 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
149 };
150
151 /* I2C pinmux */
152 gen1-i2c {
153 nvidia,pins = "gen1_i2c_scl_pc4",
154 "gen1_i2c_sda_pc5";
155 nvidia,function = "i2c1";
156 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
157 nvidia,tristate = <TEGRA_PIN_DISABLE>;
158 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
159 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
160 nvidia,lock = <0>;
161 };
162 gen2-i2c {
163 nvidia,pins = "gen2_i2c_scl_pt5",
164 "gen2_i2c_sda_pt6";
165 nvidia,function = "i2c2";
166 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
167 nvidia,tristate = <TEGRA_PIN_DISABLE>;
168 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
169 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
170 nvidia,lock = <0>;
171 };
172 cam-i2c {
173 nvidia,pins = "cam_i2c_scl_pbb1",
174 "cam_i2c_sda_pbb2";
175 nvidia,function = "i2c3";
176 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
177 nvidia,tristate = <TEGRA_PIN_DISABLE>;
178 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
179 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
180 nvidia,lock = <0>;
181 };
182 ddc-i2c {
183 nvidia,pins = "ddc_scl_pv4",
184 "ddc_sda_pv5";
185 nvidia,function = "i2c4";
186 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
187 nvidia,tristate = <TEGRA_PIN_DISABLE>;
188 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
189 nvidia,lock = <0>;
190 };
191 pwr-i2c {
192 nvidia,pins = "pwr_i2c_scl_pz6",
193 "pwr_i2c_sda_pz7";
194 nvidia,function = "i2cpwr";
195 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
196 nvidia,tristate = <TEGRA_PIN_DISABLE>;
197 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
198 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
199 nvidia,lock = <0>;
200 };
201
202 /* HDMI pinmux */
203 hdmi-cec {
204 nvidia,pins = "hdmi_cec_pee3";
205 nvidia,function = "cec";
206 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
207 nvidia,tristate = <TEGRA_PIN_DISABLE>;
208 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
209 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
210 };
211 hdmi-int {
212 nvidia,pins = "hdmi_int_pn7";
213 nvidia,function = "rsvd1";
214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
215 nvidia,tristate = <TEGRA_PIN_ENABLE>;
216 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
217 };
218
219 /* UART-B */
220 uartb-txd-rts {
221 nvidia,pins = "uart2_txd_pc2",
222 "uart2_rts_n_pj6";
223 nvidia,function = "uartb";
224 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
225 nvidia,tristate = <TEGRA_PIN_DISABLE>;
226 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
227 };
228 uartb-rxd-cts {
229 nvidia,pins = "uart2_rxd_pc3",
230 "uart2_cts_n_pj5";
231 nvidia,function = "uartb";
232 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
233 nvidia,tristate = <TEGRA_PIN_DISABLE>;
234 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
235 };
236
237 /* UART-C */
238 uartc-rxd-cts {
239 nvidia,pins = "uart3_cts_n_pa1",
240 "uart3_rxd_pw7";
241 nvidia,function = "uartc";
242 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
243 nvidia,tristate = <TEGRA_PIN_DISABLE>;
244 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
245 };
246 uartc-txd-rts {
247 nvidia,pins = "uart3_rts_n_pc0",
248 "uart3_txd_pw6";
249 nvidia,function = "uartc";
250 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
251 nvidia,tristate = <TEGRA_PIN_DISABLE>;
252 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
253 };
254
255 /* UART-D */
256 uartd-rxd {
257 nvidia,pins = "gmi_a17_pb0";
258 nvidia,function = "uartd";
259 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
260 nvidia,tristate = <TEGRA_PIN_DISABLE>;
261 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
262 };
263 uartd-txd {
264 nvidia,pins = "gmi_a16_pj7";
265 nvidia,function = "uartd";
266 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
267 nvidia,tristate = <TEGRA_PIN_DISABLE>;
268 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
269 };
270
271 /* I2S pinmux */
272 dap-i2s0 {
273 nvidia,pins = "dap1_fs_pn0",
274 "dap1_din_pn1",
275 "dap1_dout_pn2",
276 "dap1_sclk_pn3";
277 nvidia,function = "i2s0";
278 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
279 nvidia,tristate = <TEGRA_PIN_DISABLE>;
280 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
281 };
282 dap-i2s1 {
283 nvidia,pins = "dap2_fs_pa2",
284 "dap2_sclk_pa3",
285 "dap2_din_pa4",
286 "dap2_dout_pa5";
287 nvidia,function = "i2s1";
288 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
289 nvidia,tristate = <TEGRA_PIN_DISABLE>;
290 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
291 };
292 dap-i2s2 {
293 nvidia,pins = "dap3_fs_pp0",
294 "dap3_din_pp1",
295 "dap3_dout_pp2";
296 nvidia,function = "i2s2";
297 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
298 nvidia,tristate = <TEGRA_PIN_DISABLE>;
299 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
300 };
301 dap3-sclk {
302 nvidia,pins = "dap3_sclk_pp3";
303 nvidia,function = "i2s2";
304 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
305 nvidia,tristate = <TEGRA_PIN_ENABLE>;
306 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
307 };
308 dap-i2s3 {
309 nvidia,pins = "dap4_fs_pp4",
310 "dap4_din_pp5",
311 "dap4_dout_pp6",
312 "dap4_sclk_pp7";
313 nvidia,function = "i2s3";
314 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
315 nvidia,tristate = <TEGRA_PIN_DISABLE>;
316 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
317 };
318
319 /* PCI-e pinmux */
320 pex-l2-rst-n {
321 nvidia,pins = "pex_l2_rst_n_pcc6",
322 "pex_l2_clkreq_n_pcc7";
323 nvidia,function = "pcie";
324 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
325 nvidia,tristate = <TEGRA_PIN_DISABLE>;
326 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
327 };
328 pex-l0-prsnt-n {
329 nvidia,pins = "pex_l0_prsnt_n_pdd0",
330 "pex_l0_rst_n_pdd1",
331 "pex_l0_clkreq_n_pdd2",
332 "pex_l1_prsnt_n_pdd4",
333 "pex_l1_rst_n_pdd5",
334 "pex_l1_clkreq_n_pdd6";
335 nvidia,function = "pcie";
336 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
337 nvidia,tristate = <TEGRA_PIN_ENABLE>;
338 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
339 };
340 pex-wake-n {
341 nvidia,pins = "pex_wake_n_pdd3",
342 "pex_l2_prsnt_n_pdd7";
343 nvidia,function = "pcie";
344 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
345 nvidia,tristate = <TEGRA_PIN_DISABLE>;
346 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
347 };
348
349 /* SPI pinmux */
350 spi1-mosi {
351 nvidia,pins = "spi1_mosi_px4",
352 "spi1_sck_px5",
353 "spi1_cs0_n_px6",
354 "spi1_miso_px7";
355 nvidia,function = "spi1";
356 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
357 nvidia,tristate = <TEGRA_PIN_DISABLE>;
358 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
359 };
360 spi2-mosi {
361 nvidia,pins = "spi2_mosi_px0",
362 "spi2_miso_px1",
363 "spi2_cs1_n_pw2",
364 "spi2_cs2_n_pw3",
365 "ulpi_data7_po0",
366 "ulpi_data4_po5",
367 "ulpi_data5_po6",
368 "ulpi_data6_po7";
369 nvidia,function = "spi2";
370 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
371 nvidia,tristate = <TEGRA_PIN_DISABLE>;
372 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
373 };
374 spi2-sck {
375 nvidia,pins = "spi2_sck_px2";
376 nvidia,function = "spi2";
377 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
378 nvidia,tristate = <TEGRA_PIN_DISABLE>;
379 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
380 };
381
382 /* Display A pinmux */
383 lcd-pwr0 {
384 nvidia,pins = "lcd_pwr0_pb2",
385 "lcd_pwr1_pc1",
386 "lcd_pwr2_pc6",
387 "lcd_m1_pw1",
388 "lcd_dc0_pn6";
389 nvidia,function = "displaya";
390 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
391 nvidia,tristate = <TEGRA_PIN_DISABLE>;
392 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
393 };
394 lcd-pclk {
395 nvidia,pins = "lcd_pclk_pb3",
396 "lcd_dc1_pd2",
397 "lcd_d0_pe0",
398 "lcd_d1_pe1",
399 "lcd_d2_pe2",
400 "lcd_d3_pe3",
401 "lcd_d4_pe4",
402 "lcd_d5_pe5",
403 "lcd_d6_pe6",
404 "lcd_d7_pe7",
405 "lcd_d8_pf0",
406 "lcd_d9_pf1",
407 "lcd_d10_pf2",
408 "lcd_d11_pf3",
409 "lcd_d12_pf4",
410 "lcd_d13_pf5",
411 "lcd_d14_pf6",
412 "lcd_d15_pf7",
413 "lcd_de_pj1",
414 "lcd_hsync_pj3",
415 "lcd_vsync_pj4",
416 "lcd_d16_pm0",
417 "lcd_d17_pm1",
418 "lcd_d18_pm2",
419 "lcd_d19_pm3",
420 "lcd_d20_pm4",
421 "lcd_d21_pm5",
422 "lcd_d22_pm6",
423 "lcd_d23_pm7",
424 "lcd_cs0_n_pn4",
425 "lcd_sdout_pn5",
426 "lcd_cs1_n_pw0",
427 "lcd_sdin_pz2",
428 "lcd_sck_pz4";
429 nvidia,function = "displaya";
430 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
431 nvidia,tristate = <TEGRA_PIN_DISABLE>;
432 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
433 };
434 lcd-wr-n {
435 nvidia,pins = "lcd_wr_n_pz3";
436 nvidia,function = "displaya";
437 nvidia,pull = <TEGRA_PIN_PULL_UP>;
438 nvidia,tristate = <TEGRA_PIN_DISABLE>;
439 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
440 };
441
442 clk-32k-out {
443 nvidia,pins = "clk_32k_out_pa0";
444 nvidia,function = "blink";
445 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
446 nvidia,tristate = <TEGRA_PIN_DISABLE>;
447 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
448 };
449 sys-clk-req {
450 nvidia,pins = "sys_clk_req_pz5";
451 nvidia,function = "sysclk";
452 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
453 nvidia,tristate = <TEGRA_PIN_DISABLE>;
454 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
455 };
456 owr {
457 nvidia,pins = "owr";
458 nvidia,function = "owr";
459 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
460 nvidia,tristate = <TEGRA_PIN_DISABLE>;
461 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
462 };
463
464 /* KBC pinmux */
465 kb-col0 {
466 nvidia,pins = "kb_col0_pq0",
467 "kb_col1_pq1",
468 "kb_col2_pq2",
469 "kb_col3_pq3",
470 "kb_row0_pr0",
471 "kb_row1_pr1",
472 "kb_row2_pr2";
473 nvidia,function = "kbc";
474 nvidia,pull = <TEGRA_PIN_PULL_UP>;
475 nvidia,tristate = <TEGRA_PIN_DISABLE>;
476 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
477 };
478 kb-col4 {
479 nvidia,pins = "kb_col4_pq4",
480 "kb_col5_pq5",
481 "kb_col6_pq6",
482 "kb_col7_pq7",
483 "kb_row12_ps4",
484 "kb_row13_ps5",
485 "kb_row14_ps6";
486 nvidia,function = "kbc";
487 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
488 nvidia,tristate = <TEGRA_PIN_ENABLE>;
489 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
490 };
491 kb-row3 {
492 nvidia,pins = "kb_row3_pr3",
493 "kb_row4_pr4",
494 "kb_row5_pr5",
495 "kb_row6_pr6",
496 "kb_row7_pr7",
497 "kb_row8_ps0",
498 "kb_row9_ps1",
499 "kb_row10_ps2",
500 "kb_row15_ps7";
501 nvidia,function = "kbc";
502 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
503 nvidia,tristate = <TEGRA_PIN_DISABLE>;
504 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
505 };
506 kb-row11 {
507 nvidia,pins = "kb_row11_ps3";
508 nvidia,function = "kbc";
509 nvidia,pull = <TEGRA_PIN_PULL_UP>;
510 nvidia,tristate = <TEGRA_PIN_ENABLE>;
511 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
512 };
513
514 /* VI pinmux */
515 vi-d0 {
516 nvidia,pins = "vi_d0_pt4",
517 "vi_d1_pd5",
518 "vi_d10_pt2",
519 "vi_d11_pt3";
520 nvidia,function = "vi";
521 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
522 nvidia,tristate = <TEGRA_PIN_ENABLE>;
523 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
524 };
525 vi-d2 {
526 nvidia,pins = "vi_d2_pl0",
527 "vi_d3_pl1",
528 "vi_d4_pl2",
529 "vi_d5_pl3",
530 "vi_d6_pl4",
531 "vi_d7_pl5",
532 "vi_d8_pl6",
533 "vi_d9_pl7",
534 "vi_vsync_pd6",
535 "vi_hsync_pd7",
536 "vi_pclk_pt0",
537 "vi_mclk_pt1";
538 nvidia,function = "vi";
539 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
540 nvidia,tristate = <TEGRA_PIN_DISABLE>;
541 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
542 };
543
544 spdif-out {
545 nvidia,pins = "spdif_out_pk5";
546 nvidia,function = "spdif";
547 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
548 nvidia,tristate = <TEGRA_PIN_DISABLE>;
549 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
550 };
551 spdif-in {
552 nvidia,pins = "spdif_in_pk6";
553 nvidia,function = "spdif";
554 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
555 nvidia,tristate = <TEGRA_PIN_DISABLE>;
556 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
557 };
558
559 /* ULPI pinmux */
560 ulpi-clk {
561 nvidia,pins = "ulpi_clk_py0",
562 "ulpi_data0_po1",
563 "ulpi_data1_po2",
564 "ulpi_data2_po3",
565 "ulpi_data3_po4";
566 nvidia,function = "ulpi";
567 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
568 nvidia,tristate = <TEGRA_PIN_ENABLE>;
569 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
570 };
571 ulpi-dir {
572 nvidia,pins = "ulpi_dir_py1",
573 "ulpi_nxt_py2",
574 "ulpi_stp_py3";
575 nvidia,function = "ulpi";
576 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
577 nvidia,tristate = <TEGRA_PIN_DISABLE>;
578 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
579 };
580
581 /* PORT U */
582 pu0 {
583 nvidia,pins = "pu0";
584 nvidia,function = "rsvd4";
585 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
586 nvidia,tristate = <TEGRA_PIN_DISABLE>;
587 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
588 };
589 pu1 {
590 nvidia,pins = "pu1";
591 nvidia,function = "rsvd1";
592 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
593 nvidia,tristate = <TEGRA_PIN_DISABLE>;
594 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
595 };
596 pu2 {
597 nvidia,pins = "pu2";
598 nvidia,function = "rsvd1";
599 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
600 nvidia,tristate = <TEGRA_PIN_DISABLE>;
601 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
602 };
603 pu3 {
604 nvidia,pins = "pu3";
605 nvidia,function = "rsvd4";
606 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
607 nvidia,tristate = <TEGRA_PIN_DISABLE>;
608 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
609 };
610 pu4 {
611 nvidia,pins = "pu4";
612 nvidia,function = "pwm1";
613 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
614 nvidia,tristate = <TEGRA_PIN_DISABLE>;
615 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
616 };
617 pu5 {
618 nvidia,pins = "pu5";
619 nvidia,function = "pwm2";
620 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
621 nvidia,tristate = <TEGRA_PIN_DISABLE>;
622 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
623 };
624 pu6 {
625 nvidia,pins = "pu6";
626 nvidia,function = "rsvd4";
627 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
628 nvidia,tristate = <TEGRA_PIN_DISABLE>;
629 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
630 };
631
632 jtag-rtck-pu7 {
633 nvidia,pins = "jtag_rtck_pu7";
634 nvidia,function = "rtck";
635 nvidia,pull = <TEGRA_PIN_PULL_UP>;
636 nvidia,tristate = <TEGRA_PIN_DISABLE>;
637 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
638 };
639
640 /* PORT V */
641 pv0 {
642 nvidia,pins = "pv0";
643 nvidia,function = "rsvd1";
644 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
645 nvidia,tristate = <TEGRA_PIN_DISABLE>;
646 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
647 };
648 pv1 {
649 nvidia,pins = "pv1";
650 nvidia,function = "rsvd1";
651 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
652 nvidia,tristate = <TEGRA_PIN_DISABLE>;
653 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
654 };
655 pv2 {
656 nvidia,pins = "pv2";
657 nvidia,function = "owr";
658 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
659 nvidia,tristate = <TEGRA_PIN_ENABLE>;
660 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
661 };
662 pv3 {
663 nvidia,pins = "pv3";
664 nvidia,function = "rsvd2";
665 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
666 nvidia,tristate = <TEGRA_PIN_ENABLE>;
667 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
668 };
669
670 /* PORT BB */
671 pbb0 {
672 nvidia,pins = "pbb0";
673 nvidia,function = "rsvd2";
674 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
675 nvidia,tristate = <TEGRA_PIN_DISABLE>;
676 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
677 };
678 pbb3 {
679 nvidia,pins = "pbb3";
680 nvidia,function = "vgp3";
681 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
682 nvidia,tristate = <TEGRA_PIN_DISABLE>;
683 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
684 };
685 pbb4 {
686 nvidia,pins = "pbb4";
687 nvidia,function = "vgp4";
688 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
689 nvidia,tristate = <TEGRA_PIN_DISABLE>;
690 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
691 };
692 pbb5 {
693 nvidia,pins = "pbb5";
694 nvidia,function = "vgp5";
695 nvidia,pull = <TEGRA_PIN_PULL_UP>;
696 nvidia,tristate = <TEGRA_PIN_DISABLE>;
697 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
698 };
699 pbb6 {
700 nvidia,pins = "pbb6";
701 nvidia,function = "vgp6";
702 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
703 nvidia,tristate = <TEGRA_PIN_DISABLE>;
704 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
705 };
706 pbb7 {
707 nvidia,pins = "pbb7";
708 nvidia,function = "i2s4";
709 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
710 nvidia,tristate = <TEGRA_PIN_DISABLE>;
711 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
712 };
713
714 /* PORT CC */
715 pcc1 {
716 nvidia,pins = "pcc1";
717 nvidia,function = "rsvd2";
718 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
719 nvidia,tristate = <TEGRA_PIN_DISABLE>;
720 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
721 };
722 pcc2 {
723 nvidia,pins = "pcc2";
724 nvidia,function = "i2s4";
725 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
726 nvidia,tristate = <TEGRA_PIN_DISABLE>;
727 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
728 };
729
730 crt-hsync-vsync {
731 nvidia,pins = "crt_hsync_pv6",
732 "crt_vsync_pv7";
733 nvidia,function = "crt";
734 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
735 nvidia,tristate = <TEGRA_PIN_DISABLE>;
736 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
737 };
738
739 clk1-out {
740 nvidia,pins = "clk1_out_pw4";
741 nvidia,function = "extperiph1";
742 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
743 nvidia,tristate = <TEGRA_PIN_DISABLE>;
744 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
745 };
746 clk1-req {
747 nvidia,pins = "clk1_req_pee2";
748 nvidia,function = "dap";
749 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
750 nvidia,tristate = <TEGRA_PIN_ENABLE>;
751 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
752 };
753 clk2-out {
754 nvidia,pins = "clk2_out_pw5";
755 nvidia,function = "extperiph2";
756 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
757 nvidia,tristate = <TEGRA_PIN_DISABLE>;
758 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
759 };
760 clk2-req {
761 nvidia,pins = "clk2_req_pcc5";
762 nvidia,function = "dap";
763 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
764 nvidia,tristate = <TEGRA_PIN_DISABLE>;
765 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
766 };
767 clk3-out {
768 nvidia,pins = "clk3_out_pee0";
769 nvidia,function = "extperiph3";
770 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
771 nvidia,tristate = <TEGRA_PIN_DISABLE>;
772 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
773 };
774 clk3-req {
775 nvidia,pins = "clk3_req_pee1";
776 nvidia,function = "dev3";
777 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
778 nvidia,tristate = <TEGRA_PIN_ENABLE>;
779 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
780 };
781
782 /* GMI pinmux */
783 gmi-a18 {
784 nvidia,pins = "gmi_a18_pb1";
785 nvidia,function = "spi4";
786 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
787 nvidia,tristate = <TEGRA_PIN_DISABLE>;
788 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
789 };
790 gmi-wp-n {
791 nvidia,pins = "gmi_wp_n_pc7",
792 "gmi_wait_pi7";
793 nvidia,function = "rsvd1";
794 nvidia,pull = <TEGRA_PIN_PULL_UP>;
795 nvidia,tristate = <TEGRA_PIN_DISABLE>;
796 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
797 };
798 gmi-ad0 {
799 nvidia,pins = "gmi_ad0_pg0",
800 "gmi_ad1_pg1",
801 "gmi_cs3_n_pk4";
802 nvidia,function = "rsvd1";
803 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
804 nvidia,tristate = <TEGRA_PIN_DISABLE>;
805 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
806 };
807 gmi-ad2 {
808 nvidia,pins = "gmi_ad2_pg2",
809 "gmi_ad3_pg3",
810 "gmi_ad6_pg6",
811 "gmi_ad7_pg7";
812 nvidia,function = "rsvd1";
813 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
814 nvidia,tristate = <TEGRA_PIN_DISABLE>;
815 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
816 };
817 gmi-ad4 {
818 nvidia,pins = "gmi_ad4_pg4",
819 "gmi_ad5_pg5",
820 "gmi_ad12_ph4",
821 "gmi_ad13_ph5",
822 "gmi_ad14_ph6",
823 "gmi_ad15_ph7",
824 "gmi_dqs_pi2",
825 "gmi_cs0_n_pj0",
826 "gmi_cs4_n_pk2";
827 nvidia,function = "rsvd1";
828 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
829 nvidia,tristate = <TEGRA_PIN_DISABLE>;
830 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
831 };
832 gmi-ad8 {
833 nvidia,pins = "gmi_ad8_ph0";
834 nvidia,function = "pwm0";
835 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
836 nvidia,tristate = <TEGRA_PIN_DISABLE>;
837 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
838 };
839 gmi-ad9 {
840 nvidia,pins = "gmi_ad9_ph1";
841 nvidia,function = "rsvd4";
842 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
843 nvidia,tristate = <TEGRA_PIN_DISABLE>;
844 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
845 };
846 gmi-ad10 {
847 nvidia,pins = "gmi_ad10_ph2";
848 nvidia,function = "pwm2";
849 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
850 nvidia,tristate = <TEGRA_PIN_DISABLE>;
851 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
852 };
853 gmi-ad11 {
854 nvidia,pins = "gmi_ad11_ph3";
855 nvidia,function = "pwm3";
856 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
857 nvidia,tristate = <TEGRA_PIN_DISABLE>;
858 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
859 };
860 gmi-wr-n {
861 nvidia,pins = "gmi_wr_n_pi0",
862 "gmi_oe_n_pi1",
863 "gmi_cs1_n_pj2",
864 "gmi_adv_n_pk0";
865 nvidia,function = "rsvd1";
866 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
867 nvidia,tristate = <TEGRA_PIN_ENABLE>;
868 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
869 };
870 gmi-cs6-n {
871 nvidia,pins = "gmi_cs6_n_pi3",
872 "gmi_cs7_n_pi6",
873 "gmi_clk_pk1";
874 nvidia,function = "nand";
875 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
876 nvidia,tristate = <TEGRA_PIN_ENABLE>;
877 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
878 };
879 gmi-rst-n {
880 nvidia,pins = "gmi_rst_n_pi4";
881 nvidia,function = "nand";
882 nvidia,pull = <TEGRA_PIN_PULL_UP>;
883 nvidia,tristate = <TEGRA_PIN_DISABLE>;
884 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
885 };
886 gmi-cs2-n {
887 nvidia,pins = "gmi_cs2_n_pk3";
888 nvidia,function = "rsvd1";
889 nvidia,pull = <TEGRA_PIN_PULL_UP>;
890 nvidia,tristate = <TEGRA_PIN_DISABLE>;
891 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
892 };
893 gmi-a19 {
894 nvidia,pins = "gmi_a19_pk7";
895 nvidia,function = "gmi";
896 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
897 nvidia,tristate = <TEGRA_PIN_DISABLE>;
898 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
899 };
900
901 /* GPIO power/drive control */
902 drive-dap2 {
903 nvidia,pins = "drive_dap2",
904 "drive_dbg",
905 "drive_at5",
906 "drive_gme",
907 "drive_ddc",
908 "drive_ao1",
909 "drive_uart3";
910 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
911 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
912 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
913 nvidia,pull-down-strength = <31>;
914 nvidia,pull-up-strength = <31>;
915 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
916 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
917 };
918
919 drive-sdio1 {
920 nvidia,pins = "drive_sdio1",
921 "drive_sdio3";
922 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
923 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
924 nvidia,pull-down-strength = <46>;
925 nvidia,pull-up-strength = <42>;
926 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
927 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
928 };
929 };
930 };
931
932 uartd: serial@70006300 {
933 status = "okay";
934 };
935
936 pwm: pwm@7000a000 {
937 status = "okay";
938 };
939
940 pwr_i2c: i2c@7000d000 {
941 status = "okay";
942 clock-frequency = <400000>;
943
944 pmic: max77663@3c {
945 compatible = "maxim,max77663";
946 reg = <0x3c>;
947
948 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
949 #interrupt-cells = <2>;
950 interrupt-controller;
951
952 #gpio-cells = <2>;
953 gpio-controller;
954
955 system-power-controller;
956
957 regulators {
958 vdd_1v8_vio: sd2 {
959 regulator-name = "vdd_1v8_gen";
960 regulator-min-microvolt = <1800000>;
961 regulator-max-microvolt = <1800000>;
962 regulator-always-on;
963 regulator-boot-on;
964 };
965
966 vcore_emmc: ldo3 {
967 regulator-name = "vcore_emmc";
968 regulator-min-microvolt = <2850000>;
969 regulator-max-microvolt = <3100000>;
970 regulator-boot-on;
971 };
972
973 vddio_usd: ldo6 {
974 regulator-name = "vddio_usd";
975 regulator-min-microvolt = <1800000>;
976 regulator-max-microvolt = <3300000>;
977 regulator-always-on;
978 regulator-boot-on;
979 };
980 };
981 };
982 };
983
984 sdmmc1: sdhci@78000000 {
985 status = "okay";
986 bus-width = <4>;
987
988 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
989 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
990
991 vmmc-supply = <&vdd_usd>;
992 vqmmc-supply = <&vddio_usd>;
993 };
994
995 sdmmc4: sdhci@78000600 {
996 status = "okay";
997 bus-width = <8>;
998 non-removable;
999
1000 vmmc-supply = <&vcore_emmc>;
1001 vqmmc-supply = <&vdd_1v8_vio>;
1002 };
1003
1004 micro_usb: usb@7d000000 {
1005 status = "okay";
1006 dr_mode = "otg";
1007 };
1008
1009 /* Full size USB */
1010 usb3: usb@7d008000 {
1011 status = "okay";
1012 };
1013
1014 backlight: backlight {
1015 compatible = "pwm-backlight";
1016
1017 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
1018 power-supply = <&vdd_5v0_bl>;
1019 pwms = <&pwm 0 5000000>;
1020
1021 brightness-levels = <1 35 70 105 140 175 210 255>;
1022 default-brightness-level = <5>;
1023 };
1024
1025 clk32k_in: clock-32k {
1026 compatible = "fixed-clock";
1027 #clock-cells = <0>;
1028 clock-frequency = <32768>;
1029 clock-output-names = "ref-oscillator";
1030 };
1031
1032 gpio-keys {
1033 compatible = "gpio-keys";
1034
1035 key-power {
1036 label = "Power";
1037 gpios = <&pmic EN0 GPIO_ACTIVE_HIGH>;
1038 linux,code = <KEY_ENTER>;
1039 };
1040
1041 key-volume-down {
1042 label = "Volume Down";
1043 gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
1044 linux,code = <KEY_DOWN>;
1045 };
1046
1047 key-volume-up {
1048 label = "Volume Up";
1049 gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>;
1050 linux,code = <KEY_UP>;
1051 };
1052 };
1053
1054 panel: panel {
1055 compatible = "simple-panel";
1056
1057 power-supply = <&vdd_pnl_reg>;
1058 enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>;
1059
1060 backlight = <&backlight>;
1061
1062 display-timings {
1063 timing@0 {
1064 /* 1280x800@60Hz */
1065 clock-frequency = <81750000>;
1066
1067 hactive = <800>;
1068 hfront-porch = <64>;
1069 hback-porch = <128>;
1070 hsync-len = <64>;
1071
1072 vactive = <1280>;
1073 vfront-porch = <5>;
1074 vback-porch = <2>;
1075 vsync-len = <1>;
1076 };
1077 };
1078 };
1079
1080 vdd_5v0_bl: regulator-bl {
1081 compatible = "regulator-fixed";
1082 regulator-name = "vdd_5v0_bl";
1083 regulator-min-microvolt = <5000000>;
1084 regulator-max-microvolt = <5000000>;
1085 gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
1086 enable-active-high;
1087 };
1088
1089 vdd_usd: regulator-emmc {
1090 compatible = "regulator-fixed";
1091 regulator-name = "vdd_3v3_sdmmc1";
1092 regulator-min-microvolt = <3300000>;
1093 regulator-max-microvolt = <3300000>;
1094 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
1095 enable-active-high;
1096 };
1097
1098 vdd_pnl_reg: regulator-pnl {
1099 compatible = "regulator-fixed";
1100 regulator-name = "vdd_panel";
1101 regulator-min-microvolt = <3300000>;
1102 regulator-max-microvolt = <3300000>;
1103 gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>;
1104 enable-active-high;
1105 };
1106};