developer | 2420220 | 2022-09-09 19:59:45 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2022 MediaTek Inc. All Rights Reserved. |
| 4 | * |
| 5 | * Author: SkyLake.Huang <skylake.huang@mediatek.com> |
| 6 | */ |
| 7 | |
| 8 | #include <clk.h> |
| 9 | #include <cpu_func.h> |
| 10 | #include <div64.h> |
| 11 | #include <dm.h> |
| 12 | #include <spi.h> |
| 13 | #include <spi-mem.h> |
| 14 | #include <stdbool.h> |
| 15 | #include <watchdog.h> |
| 16 | #include <dm/device.h> |
| 17 | #include <dm/device_compat.h> |
| 18 | #include <dm/devres.h> |
| 19 | #include <dm/pinctrl.h> |
| 20 | #include <linux/bitops.h> |
| 21 | #include <linux/completion.h> |
| 22 | #include <linux/dma-mapping.h> |
| 23 | #include <linux/io.h> |
| 24 | #include <linux/iopoll.h> |
Tom Rini | 5ba346a | 2022-10-28 20:27:08 -0400 | [diff] [blame] | 25 | #include <linux/sizes.h> |
developer | 2420220 | 2022-09-09 19:59:45 +0800 | [diff] [blame] | 26 | |
| 27 | #define SPI_CFG0_REG 0x0000 |
| 28 | #define SPI_CFG1_REG 0x0004 |
| 29 | #define SPI_TX_SRC_REG 0x0008 |
| 30 | #define SPI_RX_DST_REG 0x000c |
| 31 | #define SPI_TX_DATA_REG 0x0010 |
| 32 | #define SPI_RX_DATA_REG 0x0014 |
| 33 | #define SPI_CMD_REG 0x0018 |
| 34 | #define SPI_IRQ_REG 0x001c |
| 35 | #define SPI_STATUS_REG 0x0020 |
| 36 | #define SPI_PAD_SEL_REG 0x0024 |
| 37 | #define SPI_CFG2_REG 0x0028 |
| 38 | #define SPI_TX_SRC_REG_64 0x002c |
| 39 | #define SPI_RX_DST_REG_64 0x0030 |
| 40 | #define SPI_CFG3_IPM_REG 0x0040 |
| 41 | |
| 42 | #define SPI_CFG0_SCK_HIGH_OFFSET 0 |
| 43 | #define SPI_CFG0_SCK_LOW_OFFSET 8 |
| 44 | #define SPI_CFG0_CS_HOLD_OFFSET 16 |
| 45 | #define SPI_CFG0_CS_SETUP_OFFSET 24 |
| 46 | #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0 |
| 47 | #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16 |
| 48 | |
| 49 | #define SPI_CFG1_CS_IDLE_OFFSET 0 |
| 50 | #define SPI_CFG1_PACKET_LOOP_OFFSET 8 |
| 51 | #define SPI_CFG1_PACKET_LENGTH_OFFSET 16 |
| 52 | #define SPI_CFG1_GET_TICKDLY_OFFSET 29 |
| 53 | |
| 54 | #define SPI_CFG1_GET_TICKDLY_MASK GENMASK(31, 29) |
| 55 | #define SPI_CFG1_CS_IDLE_MASK 0xff |
| 56 | #define SPI_CFG1_PACKET_LOOP_MASK 0xff00 |
| 57 | #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 |
| 58 | #define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16) |
| 59 | #define SPI_CFG2_SCK_HIGH_OFFSET 0 |
| 60 | #define SPI_CFG2_SCK_LOW_OFFSET 16 |
| 61 | #define SPI_CFG2_SCK_HIGH_MASK GENMASK(15, 0) |
| 62 | #define SPI_CFG2_SCK_LOW_MASK GENMASK(31, 16) |
| 63 | |
| 64 | #define SPI_CMD_ACT BIT(0) |
| 65 | #define SPI_CMD_RESUME BIT(1) |
| 66 | #define SPI_CMD_RST BIT(2) |
| 67 | #define SPI_CMD_PAUSE_EN BIT(4) |
| 68 | #define SPI_CMD_DEASSERT BIT(5) |
| 69 | #define SPI_CMD_SAMPLE_SEL BIT(6) |
| 70 | #define SPI_CMD_CS_POL BIT(7) |
| 71 | #define SPI_CMD_CPHA BIT(8) |
| 72 | #define SPI_CMD_CPOL BIT(9) |
| 73 | #define SPI_CMD_RX_DMA BIT(10) |
| 74 | #define SPI_CMD_TX_DMA BIT(11) |
| 75 | #define SPI_CMD_TXMSBF BIT(12) |
| 76 | #define SPI_CMD_RXMSBF BIT(13) |
| 77 | #define SPI_CMD_RX_ENDIAN BIT(14) |
| 78 | #define SPI_CMD_TX_ENDIAN BIT(15) |
| 79 | #define SPI_CMD_FINISH_IE BIT(16) |
| 80 | #define SPI_CMD_PAUSE_IE BIT(17) |
| 81 | #define SPI_CMD_IPM_NONIDLE_MODE BIT(19) |
| 82 | #define SPI_CMD_IPM_SPIM_LOOP BIT(21) |
| 83 | #define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22 |
| 84 | |
| 85 | #define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22) |
| 86 | |
| 87 | #define PIN_MODE_CFG(x) ((x) / 2) |
| 88 | |
| 89 | #define SPI_CFG3_IPM_PIN_MODE_OFFSET 0 |
| 90 | #define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2) |
| 91 | #define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3) |
| 92 | #define SPI_CFG3_IPM_XMODE_EN BIT(4) |
| 93 | #define SPI_CFG3_IPM_NODATA_FLAG BIT(5) |
| 94 | #define SPI_CFG3_IPM_CMD_BYTELEN_OFFSET 8 |
| 95 | #define SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET 12 |
| 96 | #define SPI_CFG3_IPM_DUMMY_BYTELEN_OFFSET 16 |
| 97 | |
| 98 | #define SPI_CFG3_IPM_CMD_PIN_MODE_MASK GENMASK(1, 0) |
| 99 | #define SPI_CFG3_IPM_CMD_BYTELEN_MASK GENMASK(11, 8) |
| 100 | #define SPI_CFG3_IPM_ADDR_BYTELEN_MASK GENMASK(15, 12) |
| 101 | #define SPI_CFG3_IPM_DUMMY_BYTELEN_MASK GENMASK(19, 16) |
| 102 | |
| 103 | #define MT8173_SPI_MAX_PAD_SEL 3 |
| 104 | |
| 105 | #define MTK_SPI_PAUSE_INT_STATUS 0x2 |
| 106 | |
| 107 | #define MTK_SPI_IDLE 0 |
| 108 | #define MTK_SPI_PAUSED 1 |
| 109 | |
| 110 | #define MTK_SPI_MAX_FIFO_SIZE 32U |
| 111 | #define MTK_SPI_PACKET_SIZE 1024 |
| 112 | #define MTK_SPI_IPM_PACKET_SIZE SZ_64K |
| 113 | #define MTK_SPI_IPM_PACKET_LOOP SZ_256 |
| 114 | |
| 115 | #define MTK_SPI_32BITS_MASK 0xffffffff |
| 116 | |
| 117 | #define DMA_ADDR_EXT_BITS 36 |
| 118 | #define DMA_ADDR_DEF_BITS 32 |
| 119 | |
| 120 | #define CLK_TO_US(freq, clkcnt) DIV_ROUND_UP((clkcnt), (freq) / 1000000) |
| 121 | |
| 122 | /* struct mtk_spim_capability |
| 123 | * @enhance_timing: Some IC design adjust cfg register to enhance time accuracy |
| 124 | * @dma_ext: Some IC support DMA addr extension |
| 125 | * @ipm_design: The IPM IP design improves some features, and supports dual/quad mode |
| 126 | * @support_quad: Whether quad mode is supported |
| 127 | */ |
| 128 | struct mtk_spim_capability { |
| 129 | bool enhance_timing; |
| 130 | bool dma_ext; |
| 131 | bool ipm_design; |
| 132 | bool support_quad; |
| 133 | }; |
| 134 | |
| 135 | /* struct mtk_spim_priv |
| 136 | * @base: Base address of the spi controller |
| 137 | * @state: Controller state |
| 138 | * @sel_clk: Pad clock |
| 139 | * @spi_clk: Core clock |
developer | 9f5fbaf | 2023-07-19 17:15:54 +0800 | [diff] [blame] | 140 | * @pll_clk_rate: Controller's PLL source clock rate, which is different |
| 141 | * from SPI bus clock rate |
developer | 2420220 | 2022-09-09 19:59:45 +0800 | [diff] [blame] | 142 | * @xfer_len: Current length of data for transfer |
| 143 | * @hw_cap: Controller capabilities |
| 144 | * @tick_dly: Used to postpone SPI sampling time |
| 145 | * @sample_sel: Sample edge of MISO |
| 146 | * @dev: udevice of this spi controller |
| 147 | * @tx_dma: Tx DMA address |
| 148 | * @rx_dma: Rx DMA address |
| 149 | */ |
| 150 | struct mtk_spim_priv { |
| 151 | void __iomem *base; |
| 152 | u32 state; |
| 153 | struct clk sel_clk, spi_clk; |
developer | 9f5fbaf | 2023-07-19 17:15:54 +0800 | [diff] [blame] | 154 | u32 pll_clk_rate; |
developer | 2420220 | 2022-09-09 19:59:45 +0800 | [diff] [blame] | 155 | u32 xfer_len; |
| 156 | struct mtk_spim_capability hw_cap; |
| 157 | u32 tick_dly; |
| 158 | u32 sample_sel; |
| 159 | |
| 160 | struct device *dev; |
| 161 | dma_addr_t tx_dma; |
| 162 | dma_addr_t rx_dma; |
| 163 | }; |
| 164 | |
| 165 | static void mtk_spim_reset(struct mtk_spim_priv *priv) |
| 166 | { |
| 167 | /* set the software reset bit in SPI_CMD_REG. */ |
| 168 | setbits_le32(priv->base + SPI_CMD_REG, SPI_CMD_RST); |
| 169 | clrbits_le32(priv->base + SPI_CMD_REG, SPI_CMD_RST); |
| 170 | } |
| 171 | |
| 172 | static int mtk_spim_hw_init(struct spi_slave *slave) |
| 173 | { |
| 174 | struct udevice *bus = dev_get_parent(slave->dev); |
| 175 | struct mtk_spim_priv *priv = dev_get_priv(bus); |
| 176 | u16 cpha, cpol; |
| 177 | u32 reg_val; |
| 178 | |
| 179 | cpha = slave->mode & SPI_CPHA ? 1 : 0; |
| 180 | cpol = slave->mode & SPI_CPOL ? 1 : 0; |
| 181 | |
| 182 | if (priv->hw_cap.enhance_timing) { |
| 183 | if (priv->hw_cap.ipm_design) { |
| 184 | /* CFG3 reg only used for spi-mem, |
| 185 | * here write to default value |
| 186 | */ |
| 187 | writel(0x0, priv->base + SPI_CFG3_IPM_REG); |
| 188 | clrsetbits_le32(priv->base + SPI_CMD_REG, |
| 189 | SPI_CMD_IPM_GET_TICKDLY_MASK, |
| 190 | priv->tick_dly << |
| 191 | SPI_CMD_IPM_GET_TICKDLY_OFFSET); |
| 192 | } else { |
| 193 | clrsetbits_le32(priv->base + SPI_CFG1_REG, |
| 194 | SPI_CFG1_GET_TICKDLY_MASK, |
| 195 | priv->tick_dly << |
| 196 | SPI_CFG1_GET_TICKDLY_OFFSET); |
| 197 | } |
| 198 | } |
| 199 | |
| 200 | reg_val = readl(priv->base + SPI_CMD_REG); |
| 201 | if (priv->hw_cap.ipm_design) { |
| 202 | /* SPI transfer without idle time until packet length done */ |
| 203 | reg_val |= SPI_CMD_IPM_NONIDLE_MODE; |
| 204 | if (slave->mode & SPI_LOOP) |
| 205 | reg_val |= SPI_CMD_IPM_SPIM_LOOP; |
| 206 | else |
| 207 | reg_val &= ~SPI_CMD_IPM_SPIM_LOOP; |
| 208 | } |
| 209 | |
| 210 | if (cpha) |
| 211 | reg_val |= SPI_CMD_CPHA; |
| 212 | else |
| 213 | reg_val &= ~SPI_CMD_CPHA; |
| 214 | if (cpol) |
| 215 | reg_val |= SPI_CMD_CPOL; |
| 216 | else |
| 217 | reg_val &= ~SPI_CMD_CPOL; |
| 218 | |
| 219 | /* set the mlsbx and mlsbtx */ |
| 220 | if (slave->mode & SPI_LSB_FIRST) { |
| 221 | reg_val &= ~SPI_CMD_TXMSBF; |
| 222 | reg_val &= ~SPI_CMD_RXMSBF; |
| 223 | } else { |
| 224 | reg_val |= SPI_CMD_TXMSBF; |
| 225 | reg_val |= SPI_CMD_RXMSBF; |
| 226 | } |
| 227 | |
| 228 | /* do not reverse tx/rx endian */ |
| 229 | reg_val &= ~SPI_CMD_TX_ENDIAN; |
| 230 | reg_val &= ~SPI_CMD_RX_ENDIAN; |
| 231 | |
| 232 | if (priv->hw_cap.enhance_timing) { |
| 233 | /* set CS polarity */ |
| 234 | if (slave->mode & SPI_CS_HIGH) |
| 235 | reg_val |= SPI_CMD_CS_POL; |
| 236 | else |
| 237 | reg_val &= ~SPI_CMD_CS_POL; |
| 238 | |
| 239 | if (priv->sample_sel) |
| 240 | reg_val |= SPI_CMD_SAMPLE_SEL; |
| 241 | else |
| 242 | reg_val &= ~SPI_CMD_SAMPLE_SEL; |
| 243 | } |
| 244 | |
developer | 92aef70 | 2023-07-19 17:16:02 +0800 | [diff] [blame] | 245 | /* Disable interrupt enable for pause mode & normal mode */ |
| 246 | reg_val &= ~(SPI_CMD_PAUSE_IE | SPI_CMD_FINISH_IE); |
| 247 | |
developer | 2420220 | 2022-09-09 19:59:45 +0800 | [diff] [blame] | 248 | /* disable dma mode */ |
| 249 | reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA); |
| 250 | |
| 251 | /* disable deassert mode */ |
| 252 | reg_val &= ~SPI_CMD_DEASSERT; |
| 253 | |
| 254 | writel(reg_val, priv->base + SPI_CMD_REG); |
| 255 | |
| 256 | return 0; |
| 257 | } |
| 258 | |
| 259 | static void mtk_spim_prepare_transfer(struct mtk_spim_priv *priv, |
| 260 | u32 speed_hz) |
| 261 | { |
developer | 9f5fbaf | 2023-07-19 17:15:54 +0800 | [diff] [blame] | 262 | u32 div, sck_time, cs_time, reg_val; |
developer | 2420220 | 2022-09-09 19:59:45 +0800 | [diff] [blame] | 263 | |
developer | 9f5fbaf | 2023-07-19 17:15:54 +0800 | [diff] [blame] | 264 | if (speed_hz <= priv->pll_clk_rate / 4) |
| 265 | div = DIV_ROUND_UP(priv->pll_clk_rate, speed_hz); |
developer | 2420220 | 2022-09-09 19:59:45 +0800 | [diff] [blame] | 266 | else |
| 267 | div = 4; |
| 268 | |
| 269 | sck_time = (div + 1) / 2; |
| 270 | cs_time = sck_time * 2; |
| 271 | |
| 272 | if (priv->hw_cap.enhance_timing) { |
| 273 | reg_val = ((sck_time - 1) & 0xffff) |
| 274 | << SPI_CFG2_SCK_HIGH_OFFSET; |
| 275 | reg_val |= ((sck_time - 1) & 0xffff) |
| 276 | << SPI_CFG2_SCK_LOW_OFFSET; |
| 277 | writel(reg_val, priv->base + SPI_CFG2_REG); |
| 278 | |
| 279 | reg_val = ((cs_time - 1) & 0xffff) |
| 280 | << SPI_ADJUST_CFG0_CS_HOLD_OFFSET; |
| 281 | reg_val |= ((cs_time - 1) & 0xffff) |
| 282 | << SPI_ADJUST_CFG0_CS_SETUP_OFFSET; |
| 283 | writel(reg_val, priv->base + SPI_CFG0_REG); |
| 284 | } else { |
| 285 | reg_val = ((sck_time - 1) & 0xff) |
| 286 | << SPI_CFG0_SCK_HIGH_OFFSET; |
| 287 | reg_val |= ((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET; |
| 288 | reg_val |= ((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET; |
| 289 | reg_val |= ((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET; |
| 290 | writel(reg_val, priv->base + SPI_CFG0_REG); |
| 291 | } |
| 292 | |
| 293 | reg_val = readl(priv->base + SPI_CFG1_REG); |
| 294 | reg_val &= ~SPI_CFG1_CS_IDLE_MASK; |
| 295 | reg_val |= ((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET; |
| 296 | writel(reg_val, priv->base + SPI_CFG1_REG); |
| 297 | } |
| 298 | |
| 299 | /** |
| 300 | * mtk_spim_setup_packet() - setup packet format. |
| 301 | * @priv: controller priv |
| 302 | * |
| 303 | * This controller sents/receives data in packets. The packet size is |
| 304 | * configurable. |
| 305 | * |
| 306 | * This function calculates the maximum packet size available for current |
| 307 | * data, and calculates the number of packets required to sent/receive data |
| 308 | * as much as possible. |
| 309 | */ |
| 310 | static void mtk_spim_setup_packet(struct mtk_spim_priv *priv) |
| 311 | { |
| 312 | u32 packet_size, packet_loop, reg_val; |
| 313 | |
| 314 | /* Calculate maximum packet size */ |
| 315 | if (priv->hw_cap.ipm_design) |
| 316 | packet_size = min_t(u32, |
| 317 | priv->xfer_len, |
| 318 | MTK_SPI_IPM_PACKET_SIZE); |
| 319 | else |
| 320 | packet_size = min_t(u32, |
| 321 | priv->xfer_len, |
| 322 | MTK_SPI_PACKET_SIZE); |
| 323 | |
| 324 | /* Calculates number of packets to sent/receive */ |
| 325 | packet_loop = priv->xfer_len / packet_size; |
| 326 | |
| 327 | reg_val = readl(priv->base + SPI_CFG1_REG); |
| 328 | if (priv->hw_cap.ipm_design) |
| 329 | reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK; |
| 330 | else |
| 331 | reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK; |
| 332 | |
| 333 | reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; |
| 334 | |
| 335 | reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK; |
| 336 | |
| 337 | reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; |
| 338 | |
| 339 | writel(reg_val, priv->base + SPI_CFG1_REG); |
| 340 | } |
| 341 | |
| 342 | static void mtk_spim_enable_transfer(struct mtk_spim_priv *priv) |
| 343 | { |
| 344 | u32 cmd; |
| 345 | |
| 346 | cmd = readl(priv->base + SPI_CMD_REG); |
| 347 | if (priv->state == MTK_SPI_IDLE) |
| 348 | cmd |= SPI_CMD_ACT; |
| 349 | else |
| 350 | cmd |= SPI_CMD_RESUME; |
| 351 | writel(cmd, priv->base + SPI_CMD_REG); |
| 352 | } |
| 353 | |
| 354 | static bool mtk_spim_supports_op(struct spi_slave *slave, |
| 355 | const struct spi_mem_op *op) |
| 356 | { |
| 357 | struct udevice *bus = dev_get_parent(slave->dev); |
| 358 | struct mtk_spim_priv *priv = dev_get_priv(bus); |
| 359 | |
| 360 | if (op->cmd.buswidth == 0 || op->cmd.buswidth > 4 || |
| 361 | op->addr.buswidth > 4 || op->dummy.buswidth > 4 || |
| 362 | op->data.buswidth > 4) |
| 363 | return false; |
| 364 | |
| 365 | if (!priv->hw_cap.support_quad && (op->cmd.buswidth > 2 || |
| 366 | op->addr.buswidth > 2 || op->dummy.buswidth > 2 || |
| 367 | op->data.buswidth > 2)) |
| 368 | return false; |
| 369 | |
| 370 | if (op->addr.nbytes && op->dummy.nbytes && |
| 371 | op->addr.buswidth != op->dummy.buswidth) |
| 372 | return false; |
| 373 | |
| 374 | if (op->addr.nbytes + op->dummy.nbytes > 16) |
| 375 | return false; |
| 376 | |
| 377 | if (op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { |
| 378 | if (op->data.nbytes / MTK_SPI_IPM_PACKET_SIZE > |
| 379 | MTK_SPI_IPM_PACKET_LOOP || |
| 380 | op->data.nbytes % MTK_SPI_IPM_PACKET_SIZE != 0) |
| 381 | return false; |
| 382 | } |
| 383 | |
| 384 | return true; |
| 385 | } |
| 386 | |
| 387 | static void mtk_spim_setup_dma_xfer(struct mtk_spim_priv *priv, |
| 388 | const struct spi_mem_op *op) |
| 389 | { |
| 390 | writel((u32)(priv->tx_dma & MTK_SPI_32BITS_MASK), |
| 391 | priv->base + SPI_TX_SRC_REG); |
| 392 | |
| 393 | if (priv->hw_cap.dma_ext) |
| 394 | writel((u32)(priv->tx_dma >> 32), |
| 395 | priv->base + SPI_TX_SRC_REG_64); |
| 396 | |
| 397 | if (op->data.dir == SPI_MEM_DATA_IN) { |
| 398 | writel((u32)(priv->rx_dma & MTK_SPI_32BITS_MASK), |
| 399 | priv->base + SPI_RX_DST_REG); |
| 400 | |
| 401 | if (priv->hw_cap.dma_ext) |
| 402 | writel((u32)(priv->rx_dma >> 32), |
| 403 | priv->base + SPI_RX_DST_REG_64); |
| 404 | } |
| 405 | } |
| 406 | |
| 407 | static int mtk_spim_transfer_wait(struct spi_slave *slave, |
| 408 | const struct spi_mem_op *op) |
| 409 | { |
| 410 | struct udevice *bus = dev_get_parent(slave->dev); |
| 411 | struct mtk_spim_priv *priv = dev_get_priv(bus); |
developer | 9f5fbaf | 2023-07-19 17:15:54 +0800 | [diff] [blame] | 412 | u32 sck_l, sck_h, clk_count, reg; |
developer | 2420220 | 2022-09-09 19:59:45 +0800 | [diff] [blame] | 413 | ulong us = 1; |
| 414 | int ret = 0; |
| 415 | |
| 416 | if (op->data.dir == SPI_MEM_NO_DATA) |
| 417 | clk_count = 32; |
| 418 | else |
| 419 | clk_count = op->data.nbytes; |
| 420 | |
developer | 2420220 | 2022-09-09 19:59:45 +0800 | [diff] [blame] | 421 | sck_l = readl(priv->base + SPI_CFG2_REG) >> SPI_CFG2_SCK_LOW_OFFSET; |
| 422 | sck_h = readl(priv->base + SPI_CFG2_REG) & SPI_CFG2_SCK_HIGH_MASK; |
developer | 9f5fbaf | 2023-07-19 17:15:54 +0800 | [diff] [blame] | 423 | do_div(priv->pll_clk_rate, sck_l + sck_h + 2); |
developer | 2420220 | 2022-09-09 19:59:45 +0800 | [diff] [blame] | 424 | |
developer | 9f5fbaf | 2023-07-19 17:15:54 +0800 | [diff] [blame] | 425 | us = CLK_TO_US(priv->pll_clk_rate, clk_count * 8); |
developer | 2420220 | 2022-09-09 19:59:45 +0800 | [diff] [blame] | 426 | us += 1000 * 1000; /* 1s tolerance */ |
| 427 | |
| 428 | if (us > UINT_MAX) |
| 429 | us = UINT_MAX; |
| 430 | |
| 431 | ret = readl_poll_timeout(priv->base + SPI_STATUS_REG, reg, |
| 432 | reg & 0x1, us); |
| 433 | if (ret < 0) { |
| 434 | dev_err(priv->dev, "transfer timeout, val: 0x%lx\n", us); |
| 435 | return -ETIMEDOUT; |
| 436 | } |
| 437 | |
| 438 | return 0; |
| 439 | } |
| 440 | |
| 441 | static int mtk_spim_exec_op(struct spi_slave *slave, |
| 442 | const struct spi_mem_op *op) |
| 443 | { |
| 444 | struct udevice *bus = dev_get_parent(slave->dev); |
| 445 | struct mtk_spim_priv *priv = dev_get_priv(bus); |
| 446 | u32 reg_val, nio = 1, tx_size; |
| 447 | char *tx_tmp_buf; |
| 448 | char *rx_tmp_buf; |
| 449 | int i, ret = 0; |
| 450 | |
| 451 | mtk_spim_reset(priv); |
| 452 | mtk_spim_hw_init(slave); |
| 453 | mtk_spim_prepare_transfer(priv, slave->max_hz); |
| 454 | |
| 455 | reg_val = readl(priv->base + SPI_CFG3_IPM_REG); |
| 456 | /* opcode byte len */ |
| 457 | reg_val &= ~SPI_CFG3_IPM_CMD_BYTELEN_MASK; |
| 458 | reg_val |= 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET; |
| 459 | |
| 460 | /* addr & dummy byte len */ |
| 461 | if (op->addr.nbytes || op->dummy.nbytes) |
| 462 | reg_val |= (op->addr.nbytes + op->dummy.nbytes) << |
| 463 | SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET; |
| 464 | |
| 465 | /* data byte len */ |
| 466 | if (!op->data.nbytes) { |
| 467 | reg_val |= SPI_CFG3_IPM_NODATA_FLAG; |
| 468 | writel(0, priv->base + SPI_CFG1_REG); |
| 469 | } else { |
| 470 | reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG; |
| 471 | priv->xfer_len = op->data.nbytes; |
| 472 | mtk_spim_setup_packet(priv); |
| 473 | } |
| 474 | |
| 475 | if (op->addr.nbytes || op->dummy.nbytes) { |
| 476 | if (op->addr.buswidth == 1 || op->dummy.buswidth == 1) |
| 477 | reg_val |= SPI_CFG3_IPM_XMODE_EN; |
| 478 | else |
| 479 | reg_val &= ~SPI_CFG3_IPM_XMODE_EN; |
| 480 | } |
| 481 | |
| 482 | if (op->addr.buswidth == 2 || |
| 483 | op->dummy.buswidth == 2 || |
| 484 | op->data.buswidth == 2) |
| 485 | nio = 2; |
| 486 | else if (op->addr.buswidth == 4 || |
| 487 | op->dummy.buswidth == 4 || |
| 488 | op->data.buswidth == 4) |
| 489 | nio = 4; |
| 490 | |
| 491 | reg_val &= ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK; |
| 492 | reg_val |= PIN_MODE_CFG(nio) << SPI_CFG3_IPM_PIN_MODE_OFFSET; |
| 493 | |
| 494 | reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; |
| 495 | if (op->data.dir == SPI_MEM_DATA_IN) |
| 496 | reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; |
| 497 | else |
| 498 | reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR; |
| 499 | writel(reg_val, priv->base + SPI_CFG3_IPM_REG); |
| 500 | |
| 501 | tx_size = 1 + op->addr.nbytes + op->dummy.nbytes; |
| 502 | if (op->data.dir == SPI_MEM_DATA_OUT) |
| 503 | tx_size += op->data.nbytes; |
| 504 | |
| 505 | tx_size = max(tx_size, (u32)32); |
| 506 | |
| 507 | /* Fill up tx data */ |
| 508 | tx_tmp_buf = kzalloc(tx_size, GFP_KERNEL); |
| 509 | if (!tx_tmp_buf) { |
| 510 | ret = -ENOMEM; |
| 511 | goto exit; |
| 512 | } |
| 513 | |
| 514 | tx_tmp_buf[0] = op->cmd.opcode; |
| 515 | |
| 516 | if (op->addr.nbytes) { |
| 517 | for (i = 0; i < op->addr.nbytes; i++) |
| 518 | tx_tmp_buf[i + 1] = op->addr.val >> |
| 519 | (8 * (op->addr.nbytes - i - 1)); |
| 520 | } |
| 521 | |
| 522 | if (op->dummy.nbytes) |
| 523 | memset(tx_tmp_buf + op->addr.nbytes + 1, 0xff, |
| 524 | op->dummy.nbytes); |
| 525 | |
| 526 | if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) |
| 527 | memcpy(tx_tmp_buf + op->dummy.nbytes + op->addr.nbytes + 1, |
| 528 | op->data.buf.out, op->data.nbytes); |
| 529 | /* Finish filling up tx data */ |
| 530 | |
| 531 | priv->tx_dma = dma_map_single(tx_tmp_buf, tx_size, DMA_TO_DEVICE); |
| 532 | if (dma_mapping_error(priv->dev, priv->tx_dma)) { |
| 533 | ret = -ENOMEM; |
| 534 | goto tx_free; |
| 535 | } |
| 536 | |
| 537 | if (op->data.dir == SPI_MEM_DATA_IN) { |
| 538 | if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) { |
| 539 | rx_tmp_buf = kzalloc(op->data.nbytes, GFP_KERNEL); |
| 540 | if (!rx_tmp_buf) { |
| 541 | ret = -ENOMEM; |
| 542 | goto tx_unmap; |
| 543 | } |
| 544 | } else { |
| 545 | rx_tmp_buf = op->data.buf.in; |
| 546 | } |
| 547 | |
| 548 | priv->rx_dma = dma_map_single(rx_tmp_buf, op->data.nbytes, |
| 549 | DMA_FROM_DEVICE); |
| 550 | if (dma_mapping_error(priv->dev, priv->rx_dma)) { |
| 551 | ret = -ENOMEM; |
| 552 | goto rx_free; |
| 553 | } |
| 554 | } |
| 555 | |
| 556 | reg_val = readl(priv->base + SPI_CMD_REG); |
| 557 | reg_val |= SPI_CMD_TX_DMA; |
| 558 | if (op->data.dir == SPI_MEM_DATA_IN) |
| 559 | reg_val |= SPI_CMD_RX_DMA; |
| 560 | |
| 561 | writel(reg_val, priv->base + SPI_CMD_REG); |
| 562 | |
| 563 | mtk_spim_setup_dma_xfer(priv, op); |
| 564 | |
| 565 | mtk_spim_enable_transfer(priv); |
| 566 | |
| 567 | /* Wait for the interrupt. */ |
| 568 | ret = mtk_spim_transfer_wait(slave, op); |
| 569 | if (ret) |
| 570 | goto rx_unmap; |
| 571 | |
| 572 | if (op->data.dir == SPI_MEM_DATA_IN && |
| 573 | !IS_ALIGNED((size_t)op->data.buf.in, 4)) |
| 574 | memcpy(op->data.buf.in, rx_tmp_buf, op->data.nbytes); |
| 575 | |
| 576 | rx_unmap: |
| 577 | /* spi disable dma */ |
| 578 | reg_val = readl(priv->base + SPI_CMD_REG); |
| 579 | reg_val &= ~SPI_CMD_TX_DMA; |
| 580 | if (op->data.dir == SPI_MEM_DATA_IN) |
| 581 | reg_val &= ~SPI_CMD_RX_DMA; |
| 582 | writel(reg_val, priv->base + SPI_CMD_REG); |
| 583 | |
| 584 | writel(0, priv->base + SPI_TX_SRC_REG); |
| 585 | writel(0, priv->base + SPI_RX_DST_REG); |
| 586 | |
| 587 | if (op->data.dir == SPI_MEM_DATA_IN) |
| 588 | dma_unmap_single(priv->rx_dma, |
| 589 | op->data.nbytes, DMA_FROM_DEVICE); |
| 590 | rx_free: |
| 591 | if (op->data.dir == SPI_MEM_DATA_IN && |
| 592 | !IS_ALIGNED((size_t)op->data.buf.in, 4)) |
| 593 | kfree(rx_tmp_buf); |
| 594 | tx_unmap: |
| 595 | dma_unmap_single(priv->tx_dma, |
| 596 | tx_size, DMA_TO_DEVICE); |
| 597 | tx_free: |
| 598 | kfree(tx_tmp_buf); |
| 599 | exit: |
| 600 | return ret; |
| 601 | } |
| 602 | |
| 603 | static int mtk_spim_adjust_op_size(struct spi_slave *slave, |
| 604 | struct spi_mem_op *op) |
| 605 | { |
| 606 | int opcode_len; |
| 607 | |
| 608 | if (!op->data.nbytes) |
| 609 | return 0; |
| 610 | |
| 611 | if (op->data.dir != SPI_MEM_NO_DATA) { |
| 612 | opcode_len = 1 + op->addr.nbytes + op->dummy.nbytes; |
| 613 | if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { |
| 614 | op->data.nbytes = MTK_SPI_IPM_PACKET_SIZE - opcode_len; |
| 615 | /* force data buffer dma-aligned. */ |
| 616 | op->data.nbytes -= op->data.nbytes % 4; |
| 617 | } |
| 618 | } |
| 619 | |
| 620 | return 0; |
| 621 | } |
| 622 | |
| 623 | static int mtk_spim_get_attr(struct mtk_spim_priv *priv, struct udevice *dev) |
| 624 | { |
| 625 | int ret; |
| 626 | |
| 627 | priv->hw_cap.enhance_timing = dev_read_bool(dev, "enhance_timing"); |
| 628 | priv->hw_cap.dma_ext = dev_read_bool(dev, "dma_ext"); |
| 629 | priv->hw_cap.ipm_design = dev_read_bool(dev, "ipm_design"); |
| 630 | priv->hw_cap.support_quad = dev_read_bool(dev, "support_quad"); |
| 631 | |
| 632 | ret = dev_read_u32(dev, "tick_dly", &priv->tick_dly); |
| 633 | if (ret < 0) |
| 634 | dev_err(priv->dev, "tick dly not set.\n"); |
| 635 | |
| 636 | ret = dev_read_u32(dev, "sample_sel", &priv->sample_sel); |
| 637 | if (ret < 0) |
| 638 | dev_err(priv->dev, "sample sel not set.\n"); |
| 639 | |
| 640 | return ret; |
| 641 | } |
| 642 | |
| 643 | static int mtk_spim_probe(struct udevice *dev) |
| 644 | { |
| 645 | struct mtk_spim_priv *priv = dev_get_priv(dev); |
| 646 | int ret; |
| 647 | |
Johan Jonker | 2f9f775 | 2023-03-13 01:32:44 +0100 | [diff] [blame] | 648 | priv->base = devfdt_get_addr_ptr(dev); |
developer | 2420220 | 2022-09-09 19:59:45 +0800 | [diff] [blame] | 649 | if (!priv->base) |
| 650 | return -EINVAL; |
| 651 | |
| 652 | mtk_spim_get_attr(priv, dev); |
| 653 | |
| 654 | ret = clk_get_by_name(dev, "sel-clk", &priv->sel_clk); |
| 655 | if (ret < 0) { |
| 656 | dev_err(dev, "failed to get sel-clk\n"); |
| 657 | return ret; |
| 658 | } |
| 659 | |
| 660 | ret = clk_get_by_name(dev, "spi-clk", &priv->spi_clk); |
| 661 | if (ret < 0) { |
| 662 | dev_err(dev, "failed to get spi-clk\n"); |
| 663 | return ret; |
| 664 | } |
| 665 | |
| 666 | clk_enable(&priv->sel_clk); |
| 667 | clk_enable(&priv->spi_clk); |
| 668 | |
developer | 9f5fbaf | 2023-07-19 17:15:54 +0800 | [diff] [blame] | 669 | priv->pll_clk_rate = clk_get_rate(&priv->spi_clk); |
| 670 | if (priv->pll_clk_rate == 0) |
| 671 | return -EINVAL; |
| 672 | |
developer | 2420220 | 2022-09-09 19:59:45 +0800 | [diff] [blame] | 673 | return 0; |
| 674 | } |
| 675 | |
| 676 | static int mtk_spim_set_speed(struct udevice *dev, uint speed) |
| 677 | { |
| 678 | return 0; |
| 679 | } |
| 680 | |
| 681 | static int mtk_spim_set_mode(struct udevice *dev, uint mode) |
| 682 | { |
| 683 | return 0; |
| 684 | } |
| 685 | |
| 686 | static const struct spi_controller_mem_ops mtk_spim_mem_ops = { |
| 687 | .adjust_op_size = mtk_spim_adjust_op_size, |
| 688 | .supports_op = mtk_spim_supports_op, |
| 689 | .exec_op = mtk_spim_exec_op |
| 690 | }; |
| 691 | |
| 692 | static const struct dm_spi_ops mtk_spim_ops = { |
| 693 | .mem_ops = &mtk_spim_mem_ops, |
| 694 | .set_speed = mtk_spim_set_speed, |
| 695 | .set_mode = mtk_spim_set_mode, |
| 696 | }; |
| 697 | |
| 698 | static const struct udevice_id mtk_spim_ids[] = { |
| 699 | { .compatible = "mediatek,ipm-spi" }, |
| 700 | {} |
| 701 | }; |
| 702 | |
| 703 | U_BOOT_DRIVER(mtk_spim) = { |
| 704 | .name = "mtk_spim", |
| 705 | .id = UCLASS_SPI, |
| 706 | .of_match = mtk_spim_ids, |
| 707 | .ops = &mtk_spim_ops, |
| 708 | .priv_auto = sizeof(struct mtk_spim_priv), |
| 709 | .probe = mtk_spim_probe, |
| 710 | }; |