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git01.mediatek.com / filogic / uboot / 1d2c14931ac8744967d760e78148717876cd2a21 / . / arch / powerpc / cpu / mpc85xx / p4080_serdes.c
blob: 463fa119c9b8b642050348ec283d6b82f1cf3eca [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Kumar Gala674e0f42010-07-12 22:51:29 -0500[diff] [blame]2/*
3 * Copyright 2009-2010 Freescale Semiconductor, Inc.
Kumar Gala674e0f42010-07-12 22:51:29 -0500[diff] [blame]4 */
5
6#include <common.h>
7#include <asm/io.h>
8#include <asm/fsl_serdes.h>
9#include <asm/processor.h>
10#include <asm/io.h>
11#include "fsl_corenet_serdes.h"
12
13static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
14 [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
15 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
16 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
17 [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
18 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
19 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
20 [0x8] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
21 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
22 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
23 [0xd] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
24 SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2,
25 XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
26 [0xe] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
27 SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2,
28 XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
29 [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
30 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2,
31 XAUI_FM2, XAUI_FM2, XAUI_FM2, NONE, NONE, NONE, NONE},
32 [0x10] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM2_DTSEC1,
33 SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
34 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
35 NONE, NONE, NONE, NONE},
36 [0x13] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
37 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
38 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
39 [0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
40 AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
41 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
42 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4},
43 [0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
44 AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
45 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4},
46 [0x1d] = {PCIE1, PCIE1, PCIE3, PCIE3, NONE, SRIO2, NONE, SRIO1,
47 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
48 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
49 [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
50 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
51 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
52 [0x25] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
53 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
54 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
55};
56
Kumar Gala779a5322010-07-13 00:39:46 -0500[diff] [blame]57#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
58uint16_t srds_lpd_b[SRDS_MAX_BANK];
59#endif
60
Kumar Gala674e0f42010-07-12 22:51:29 -0500[diff] [blame]61enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
62{
63 if (!serdes_lane_enabled(lane))
64 return NONE;
65
66 return serdes_cfg_tbl[cfg][lane];
67}
68
69int is_serdes_prtcl_valid(u32 prtcl) {
70 int i;
71
Axel Linab95b092013-05-26 15:00:30 +0800[diff] [blame]72 if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
Kumar Gala674e0f42010-07-12 22:51:29 -0500[diff] [blame]73 return 0;
74
75 for (i = 0; i < SRDS_MAX_LANES; i++) {
76 if (serdes_cfg_tbl[prtcl][i] != NONE)
77 return 1;
78 }
79
80 return 0;
81}