Andy Yan | b5e1630 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | *Copyright (c) 2018 Rockchip Electronics Co., Ltd |
| 4 | */ |
| 5 | #include <common.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 6 | #include <init.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 7 | #include <malloc.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 8 | #include <asm/global_data.h> |
Andy Yan | b5e1630 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 9 | #include <asm/io.h> |
| 10 | #include <asm/arch/grf_rk3308.h> |
John Keeping | 1cfd080 | 2022-07-14 15:18:37 +0100 | [diff] [blame^] | 11 | #include <asm/arch-rockchip/bootrom.h> |
Andy Yan | b5e1630 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 12 | #include <asm/arch-rockchip/hardware.h> |
| 13 | #include <asm/gpio.h> |
| 14 | #include <debug_uart.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 15 | #include <linux/bitops.h> |
Andy Yan | b5e1630 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 16 | |
| 17 | DECLARE_GLOBAL_DATA_PTR; |
| 18 | |
| 19 | #include <asm/armv8/mmu.h> |
| 20 | static struct mm_region rk3308_mem_map[] = { |
| 21 | { |
| 22 | .virt = 0x0UL, |
| 23 | .phys = 0x0UL, |
| 24 | .size = 0xff000000UL, |
| 25 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 26 | PTE_BLOCK_INNER_SHARE |
| 27 | }, { |
| 28 | .virt = 0xff000000UL, |
| 29 | .phys = 0xff000000UL, |
| 30 | .size = 0x01000000UL, |
| 31 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 32 | PTE_BLOCK_NON_SHARE | |
| 33 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 34 | }, { |
| 35 | /* List terminator */ |
| 36 | 0, |
| 37 | } |
| 38 | }; |
| 39 | |
| 40 | struct mm_region *mem_map = rk3308_mem_map; |
| 41 | |
| 42 | #define GRF_BASE 0xff000000 |
| 43 | #define SGRF_BASE 0xff2b0000 |
| 44 | |
| 45 | enum { |
| 46 | GPIO1C7_SHIFT = 8, |
| 47 | GPIO1C7_MASK = GENMASK(11, 8), |
| 48 | GPIO1C7_GPIO = 0, |
| 49 | GPIO1C7_UART1_RTSN, |
| 50 | GPIO1C7_UART2_TX_M0, |
| 51 | GPIO1C7_SPI2_MOSI, |
| 52 | GPIO1C7_JTAG_TMS, |
| 53 | |
| 54 | GPIO1C6_SHIFT = 4, |
| 55 | GPIO1C6_MASK = GENMASK(7, 4), |
| 56 | GPIO1C6_GPIO = 0, |
| 57 | GPIO1C6_UART1_CTSN, |
| 58 | GPIO1C6_UART2_RX_M0, |
| 59 | GPIO1C6_SPI2_MISO, |
| 60 | GPIO1C6_JTAG_TCLK, |
| 61 | |
| 62 | GPIO4D3_SHIFT = 6, |
| 63 | GPIO4D3_MASK = GENMASK(7, 6), |
| 64 | GPIO4D3_GPIO = 0, |
| 65 | GPIO4D3_SDMMC_D3, |
| 66 | GPIO4D3_UART2_TX_M1, |
| 67 | |
| 68 | GPIO4D2_SHIFT = 4, |
| 69 | GPIO4D2_MASK = GENMASK(5, 4), |
| 70 | GPIO4D2_GPIO = 0, |
| 71 | GPIO4D2_SDMMC_D2, |
| 72 | GPIO4D2_UART2_RX_M1, |
| 73 | |
| 74 | UART2_IO_SEL_SHIFT = 2, |
| 75 | UART2_IO_SEL_MASK = GENMASK(3, 2), |
| 76 | UART2_IO_SEL_M0 = 0, |
| 77 | UART2_IO_SEL_M1, |
| 78 | UART2_IO_SEL_USB, |
| 79 | |
David Wu | 770258b | 2019-12-03 19:02:50 +0800 | [diff] [blame] | 80 | GPIO2C0_SEL_SRC_CTRL_SHIFT = 11, |
| 81 | GPIO2C0_SEL_SRC_CTRL_MASK = BIT(11), |
| 82 | GPIO2C0_SEL_SRC_CTRL_IOMUX = 0, |
| 83 | GPIO2C0_SEL_SRC_CTRL_SEL_PLUS, |
| 84 | |
Andy Yan | b5e1630 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 85 | GPIO3B3_SEL_SRC_CTRL_SHIFT = 7, |
| 86 | GPIO3B3_SEL_SRC_CTRL_MASK = BIT(7), |
| 87 | GPIO3B3_SEL_SRC_CTRL_IOMUX = 0, |
| 88 | GPIO3B3_SEL_SRC_CTRL_SEL_PLUS, |
| 89 | |
| 90 | GPIO3B3_SEL_PLUS_SHIFT = 4, |
| 91 | GPIO3B3_SEL_PLUS_MASK = GENMASK(6, 4), |
| 92 | GPIO3B3_SEL_PLUS_GPIO3_B3 = 0, |
| 93 | GPIO3B3_SEL_PLUS_FLASH_ALE, |
| 94 | GPIO3B3_SEL_PLUS_EMMC_PWREN, |
| 95 | GPIO3B3_SEL_PLUS_SPI1_CLK, |
| 96 | GPIO3B3_SEL_PLUS_LCDC_D23_M1, |
| 97 | |
| 98 | GPIO3B2_SEL_SRC_CTRL_SHIFT = 3, |
| 99 | GPIO3B2_SEL_SRC_CTRL_MASK = BIT(3), |
| 100 | GPIO3B2_SEL_SRC_CTRL_IOMUX = 0, |
| 101 | GPIO3B2_SEL_SRC_CTRL_SEL_PLUS, |
| 102 | |
| 103 | GPIO3B2_SEL_PLUS_SHIFT = 0, |
| 104 | GPIO3B2_SEL_PLUS_MASK = GENMASK(2, 0), |
| 105 | GPIO3B2_SEL_PLUS_GPIO3_B2 = 0, |
| 106 | GPIO3B2_SEL_PLUS_FLASH_RDN, |
| 107 | GPIO3B2_SEL_PLUS_EMMC_RSTN, |
| 108 | GPIO3B2_SEL_PLUS_SPI1_MISO, |
| 109 | GPIO3B2_SEL_PLUS_LCDC_D22_M1, |
David Wu | 770258b | 2019-12-03 19:02:50 +0800 | [diff] [blame] | 110 | |
| 111 | I2C3_IOFUNC_SRC_CTRL_SHIFT = 10, |
| 112 | I2C3_IOFUNC_SRC_CTRL_MASK = BIT(10), |
| 113 | I2C3_IOFUNC_SRC_CTRL_SEL_PLUS = 1, |
| 114 | |
| 115 | GPIO2A3_SEL_SRC_CTRL_SHIFT = 7, |
| 116 | GPIO2A3_SEL_SRC_CTRL_MASK = BIT(7), |
| 117 | GPIO2A3_SEL_SRC_CTRL_SEL_PLUS = 1, |
| 118 | |
| 119 | GPIO2A2_SEL_SRC_CTRL_SHIFT = 3, |
| 120 | GPIO2A2_SEL_SRC_CTRL_MASK = BIT(3), |
| 121 | GPIO2A2_SEL_SRC_CTRL_SEL_PLUS = 1, |
Andy Yan | b5e1630 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 122 | }; |
| 123 | |
| 124 | enum { |
| 125 | IOVSEL3_CTRL_SHIFT = 8, |
| 126 | IOVSEL3_CTRL_MASK = BIT(8), |
| 127 | VCCIO3_SEL_BY_GPIO = 0, |
| 128 | VCCIO3_SEL_BY_IOVSEL3, |
| 129 | |
| 130 | IOVSEL3_SHIFT = 3, |
| 131 | IOVSEL3_MASK = BIT(3), |
| 132 | VCCIO3_3V3 = 0, |
| 133 | VCCIO3_1V8, |
| 134 | }; |
| 135 | |
| 136 | /* |
| 137 | * The voltage of VCCIO3(which is the voltage domain of emmc/flash/sfc |
| 138 | * interface) can indicated by GPIO0_A4 or io_vsel3. The SOC defaults |
| 139 | * use GPIO0_A4 to indicate power supply voltage for VCCIO3 by hardware, |
| 140 | * then we can switch to io_vsel3 after system power on, and release GPIO0_A4 |
| 141 | * for other usage. |
| 142 | */ |
| 143 | |
| 144 | #define GPIO0_A4 4 |
| 145 | |
John Keeping | 1cfd080 | 2022-07-14 15:18:37 +0100 | [diff] [blame^] | 146 | const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { |
| 147 | [BROM_BOOTSOURCE_EMMC] = "/mmc@ff490000", |
| 148 | [BROM_BOOTSOURCE_SD] = "/mmc@ff480000", |
| 149 | }; |
| 150 | |
Andy Yan | b5e1630 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 151 | int rk_board_init(void) |
| 152 | { |
| 153 | static struct rk3308_grf * const grf = (void *)GRF_BASE; |
| 154 | u32 val; |
| 155 | int ret; |
| 156 | |
| 157 | ret = gpio_request(GPIO0_A4, "gpio0_a4"); |
| 158 | if (ret < 0) { |
| 159 | printf("request for gpio0_a4 failed:%d\n", ret); |
| 160 | return 0; |
| 161 | } |
| 162 | |
| 163 | gpio_direction_input(GPIO0_A4); |
| 164 | |
| 165 | if (gpio_get_value(GPIO0_A4)) |
| 166 | val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT | |
| 167 | VCCIO3_1V8 << IOVSEL3_SHIFT; |
| 168 | else |
| 169 | val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT | |
| 170 | VCCIO3_3V3 << IOVSEL3_SHIFT; |
| 171 | rk_clrsetreg(&grf->soc_con0, IOVSEL3_CTRL_MASK | IOVSEL3_MASK, val); |
| 172 | |
| 173 | gpio_free(GPIO0_A4); |
| 174 | return 0; |
| 175 | } |
| 176 | |
| 177 | #if defined(CONFIG_DEBUG_UART) |
| 178 | __weak void board_debug_uart_init(void) |
| 179 | { |
| 180 | static struct rk3308_grf * const grf = (void *)GRF_BASE; |
| 181 | |
| 182 | /* Enable early UART2 channel m1 on the rk3308 */ |
| 183 | rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK, |
| 184 | UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT); |
| 185 | rk_clrsetreg(&grf->gpio4d_iomux, |
| 186 | GPIO4D3_MASK | GPIO4D2_MASK, |
| 187 | GPIO4D2_UART2_RX_M1 << GPIO4D2_SHIFT | |
| 188 | GPIO4D3_UART2_TX_M1 << GPIO4D3_SHIFT); |
| 189 | } |
| 190 | #endif |
| 191 | |
| 192 | #if defined(CONFIG_SPL_BUILD) |
| 193 | int arch_cpu_init(void) |
| 194 | { |
| 195 | static struct rk3308_sgrf * const sgrf = (void *)SGRF_BASE; |
David Wu | 770258b | 2019-12-03 19:02:50 +0800 | [diff] [blame] | 196 | static struct rk3308_grf * const grf = (void *)GRF_BASE; |
Andy Yan | b5e1630 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 197 | |
| 198 | /* Set CRYPTO SDMMC EMMC NAND SFC USB master bus to be secure access */ |
| 199 | rk_clrreg(&sgrf->con_secure0, 0x2b83); |
| 200 | |
David Wu | 770258b | 2019-12-03 19:02:50 +0800 | [diff] [blame] | 201 | /* |
| 202 | * Enable plus options to use more pinctrl functions, including |
| 203 | * GPIO2A2_PLUS, GPIO2A3_PLUS and I2C3_MULTI_SRC_PLUS. |
| 204 | */ |
| 205 | rk_clrsetreg(&grf->soc_con13, |
| 206 | I2C3_IOFUNC_SRC_CTRL_MASK | GPIO2A3_SEL_SRC_CTRL_MASK | |
| 207 | GPIO2A2_SEL_SRC_CTRL_MASK, |
| 208 | I2C3_IOFUNC_SRC_CTRL_SEL_PLUS << I2C3_IOFUNC_SRC_CTRL_SHIFT | |
| 209 | GPIO2A3_SEL_SRC_CTRL_SEL_PLUS << GPIO2A3_SEL_SRC_CTRL_SHIFT | |
| 210 | GPIO2A2_SEL_SRC_CTRL_SEL_PLUS << GPIO2A2_SEL_SRC_CTRL_SHIFT); |
| 211 | |
| 212 | /* Plus options about GPIO3B2_PLUS, GPIO3B3_PLUS and GPIO2C0_PLUS. */ |
| 213 | rk_clrsetreg(&grf->soc_con15, |
| 214 | GPIO2C0_SEL_SRC_CTRL_MASK | GPIO3B3_SEL_SRC_CTRL_MASK | |
| 215 | GPIO3B2_SEL_SRC_CTRL_MASK, |
| 216 | GPIO2C0_SEL_SRC_CTRL_SEL_PLUS << GPIO2C0_SEL_SRC_CTRL_SHIFT | |
| 217 | GPIO3B3_SEL_SRC_CTRL_SEL_PLUS << GPIO3B3_SEL_SRC_CTRL_SHIFT | |
| 218 | GPIO3B2_SEL_SRC_CTRL_SEL_PLUS << GPIO3B2_SEL_SRC_CTRL_SHIFT); |
| 219 | |
Andy Yan | b5e1630 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 220 | return 0; |
| 221 | } |
| 222 | #endif |