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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Álvaro Fernández Rojas9cc90862017-04-25 00:39:21 +02002#ifndef __ASM_MACH_BMIPS_IOREMAP_H
3#define __ASM_MACH_BMIPS_IOREMAP_H
4
5#include <linux/types.h>
6
7/*
8 * Allow physical addresses to be fixed up to help peripherals located
9 * outside the low 32-bit range -- generic pass-through version.
10 */
11static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
12 phys_addr_t size)
13{
14 return phys_addr;
15}
16
17static inline int is_bmips_internal_registers(phys_addr_t offset)
18{
Álvaro Fernández Rojase2b9ed02017-05-16 18:46:58 +020019#if defined(CONFIG_SOC_BMIPS_BCM6338) || \
20 defined(CONFIG_SOC_BMIPS_BCM6348) || \
Álvaro Fernández Rojas92da83d2017-05-16 18:39:03 +020021 defined(CONFIG_SOC_BMIPS_BCM6358)
Álvaro Fernández Rojas9cc90862017-04-25 00:39:21 +020022 if (offset >= 0xfffe0000)
23 return 1;
24#endif
25
26 return 0;
27}
28
29static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
30 unsigned long flags)
31{
32 if (is_bmips_internal_registers(offset))
33 return (void __iomem *)offset;
34
35 return NULL;
36}
37
38static inline int plat_iounmap(const volatile void __iomem *addr)
39{
40 return is_bmips_internal_registers((unsigned long)addr);
41}
42
43#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT
44
45#endif /* __ASM_MACH_BMIPS_IOREMAP_H */