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git01.mediatek.com / filogic / uboot / 1cd43a2cf248f2de6008bc0300c41a25652c5c44 / . / arch / arm / dts / rk3588-rock-5b-u-boot.dtsi
blob: 69914f4ce183668cd124db2443fc6516afd52133 [file] [log] [blame]
Eugen Hristev32f36cf2023-02-22 11:05:12 +0200[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2023 Collabora Ltd.
4 */
5
6#include "rk3588-u-boot.dtsi"
Eugen Hristev41bbad82023-05-29 13:01:35 +0300[diff] [blame]7
Jonas Karlmanadb78942023-05-18 15:39:30 +0000[diff] [blame]8&fspim2_pins {
Jonas Karlmanab956bb2024-04-22 06:28:50 +0000[diff] [blame]9 bootph-pre-ram;
10 bootph-some-ram;
Jonas Karlmanadb78942023-05-18 15:39:30 +0000[diff] [blame]11};
12
Jonas Karlmanced8be02023-04-18 16:46:41 +0000[diff] [blame]13&sdhci {
14 cap-mmc-highspeed;
Jonas Karlmanced8be02023-04-18 16:46:41 +0000[diff] [blame]15 mmc-hs200-1_8v;
Jonas Karlmanced8be02023-04-18 16:46:41 +0000[diff] [blame]16};
Eugen Hristeva856b1a2023-05-15 12:59:45 +0300[diff] [blame]17
Jonas Karlmanadb78942023-05-18 15:39:30 +0000[diff] [blame]18&sfc {
Jonas Karlmanadb78942023-05-18 15:39:30 +0000[diff] [blame]19 pinctrl-names = "default";
20 pinctrl-0 = <&fspim2_pins>;
Jonas Karlmanadb78942023-05-18 15:39:30 +0000[diff] [blame]21 status = "okay";
22
23 flash@0 {
Jonas Karlmanadb78942023-05-18 15:39:30 +0000[diff] [blame]24 compatible = "jedec,spi-nor";
25 reg = <0>;
Jonas Karlmanab956bb2024-04-22 06:28:50 +0000[diff] [blame]26 bootph-pre-ram;
27 bootph-some-ram;
Jonas Karlmanadb78942023-05-18 15:39:30 +0000[diff] [blame]28 spi-max-frequency = <24000000>;
29 spi-rx-bus-width = <4>;
30 spi-tx-bus-width = <1>;
31 };
32};
33
Eugen Hristev41bbad82023-05-29 13:01:35 +0300[diff] [blame]34&u2phy0 {
35 status = "okay";
36};
37
38&u2phy0_otg {
Eugen Hristev41bbad82023-05-29 13:01:35 +0300[diff] [blame]39 status = "okay";
40};
41
FUKAUMI Naoki61315172023-09-05 20:47:35 +0900[diff] [blame]42&u2phy1 {
Eugen Hristeva856b1a2023-05-15 12:59:45 +0300[diff] [blame]43 status = "okay";
44};
45
FUKAUMI Naoki61315172023-09-05 20:47:35 +0900[diff] [blame]46&u2phy1_otg {
Eugen Hristeva856b1a2023-05-15 12:59:45 +0300[diff] [blame]47 status = "okay";
48};
49
Jonas Karlmanf9b28c22023-10-17 17:02:11 +0000[diff] [blame]50&usbdp_phy1 {
Eugen Hristeva856b1a2023-05-15 12:59:45 +0300[diff] [blame]51 status = "okay";
52};
53
Jonas Karlmanf9b28c22023-10-17 17:02:11 +0000[diff] [blame]54&usbdp_phy1_u3 {
Eugen Hristeva856b1a2023-05-15 12:59:45 +0300[diff] [blame]55 status = "okay";
56};
57
Eugen Hristev41bbad82023-05-29 13:01:35 +0300[diff] [blame]58&usbdp_phy0 {
Eugen Hristev41bbad82023-05-29 13:01:35 +0300[diff] [blame]59 status = "okay";
Eugen Hristev41bbad82023-05-29 13:01:35 +0300[diff] [blame]60};
61
62&usbdp_phy0_u3 {
63 status = "okay";
64};
65
Jonas Karlmanf9b28c22023-10-17 17:02:11 +0000[diff] [blame]66&usb_host0_xhci {
Jonas Karlman1cd43a22024-05-04 19:43:05 +0000[diff] [blame^]67 dr_mode = "peripheral";
68 maximum-speed = "high-speed";
Eugen Hristev41bbad82023-05-29 13:01:35 +0300[diff] [blame]69 status = "okay";
Eugen Hristev41bbad82023-05-29 13:01:35 +0300[diff] [blame]70};
71
Jonas Karlmanf9b28c22023-10-17 17:02:11 +0000[diff] [blame]72&usb_host1_xhci {
Eugen Hristev41bbad82023-05-29 13:01:35 +0300[diff] [blame]73 status = "okay";
Eugen Hristev41bbad82023-05-29 13:01:35 +0300[diff] [blame]74};