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git01.mediatek.com / filogic / uboot / 1c4e7da8bd087b36b60b3eec8147e35fec129b48 / . / arch / arm / dts / zynqmp-zcu208-revA.dts
blob: 268e368b7657f73386cb811bf722ed34d98e8ba3 [file] [log] [blame]
Michal Simek31e83022019-11-25 08:38:25 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU208
4 *
Michal Simek4f1b7f62020-02-18 08:38:06 +0100[diff] [blame]5 * (C) Copyright 2017 - 2020, Xilinx, Inc.
Michal Simek31e83022019-11-25 08:38:25 +0100[diff] [blame]6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/phy/phy.h>
17
18/ {
19 model = "ZynqMP ZCU208 RevA";
20 compatible = "xlnx,zynqmp-zcu208-revA", "xlnx,zynqmp-zcu208", "xlnx,zynqmp";
21
22 aliases {
23 ethernet0 = &gem3;
24 gpio0 = &gpio;
25 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 mmc0 = &sdhci1;
28 rtc0 = &rtc;
29 serial0 = &uart0;
30 serial1 = &dcc;
31 spi0 = &qspi;
32 usb0 = &usb0;
33 };
34
35 chosen {
36 bootargs = "earlycon";
37 stdout-path = "serial0:115200n8";
38 xlnx,eeprom = &eeprom;
39 };
40
41 memory@0 {
42 device_type = "memory";
43 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
44 };
45
46 gpio-keys {
47 compatible = "gpio-keys";
48 autorepeat;
49 sw19 {
50 label = "sw19";
51 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
52 linux,code = <KEY_DOWN>;
Michal Simekf701e192020-02-18 12:06:14 +0100[diff] [blame]53 wakeup-source;
Michal Simek31e83022019-11-25 08:38:25 +0100[diff] [blame]54 autorepeat;
55 };
56 };
57
58 leds {
59 compatible = "gpio-leds";
60 heartbeat_led {
61 label = "heartbeat";
62 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
63 linux,default-trigger = "heartbeat";
64 };
65 };
66
67 ina226-vccint {
68 compatible = "iio-hwmon";
69 io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
70 };
71 ina226-vccint-io-bram-ps {
72 compatible = "iio-hwmon";
73 io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
74 };
75 ina226-vcc1v8 {
76 compatible = "iio-hwmon";
77 io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
78 };
79 ina226-vcc1v2 {
80 compatible = "iio-hwmon";
81 io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
82 };
83 ina226-vadj-fmc {
84 compatible = "iio-hwmon";
85 io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
86 };
87 ina226-mgtavcc {
88 compatible = "iio-hwmon";
89 io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
90 };
91 ina226-mgt1v2 {
92 compatible = "iio-hwmon";
93 io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
94 };
95 ina226-mgt1v8 {
96 compatible = "iio-hwmon";
97 io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
98 };
99 ina226-vccint-ams {
100 compatible = "iio-hwmon";
101 io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
102 };
103 ina226-dac-avtt {
104 compatible = "iio-hwmon";
105 io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
106 };
107 ina226-dac-avccaux {
108 compatible = "iio-hwmon";
109 io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
110 };
111 ina226-adc-avcc {
112 compatible = "iio-hwmon";
113 io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
114 };
115 ina226-adc-avccaux {
116 compatible = "iio-hwmon";
117 io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
118 };
119 ina226-dac-avcc {
120 compatible = "iio-hwmon";
121 io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
122 };
123};
124
125&dcc {
126 status = "okay";
127};
128
129&fpd_dma_chan1 {
130 status = "okay";
131};
132
133&fpd_dma_chan2 {
134 status = "okay";
135};
136
137&fpd_dma_chan3 {
138 status = "okay";
139};
140
141&fpd_dma_chan4 {
142 status = "okay";
143};
144
145&fpd_dma_chan5 {
146 status = "okay";
147};
148
149&fpd_dma_chan6 {
150 status = "okay";
151};
152
153&fpd_dma_chan7 {
154 status = "okay";
155};
156
157&fpd_dma_chan8 {
158 status = "okay";
159};
160
161&gem3 {
162 status = "okay";
163 phy-handle = <&phy0>;
164 phy-mode = "rgmii-id";
165 phy0: ethernet-phy@c {
166 reg = <0xc>;
167 ti,rx-internal-delay = <0x8>;
168 ti,tx-internal-delay = <0xa>;
169 ti,fifo-depth = <0x1>;
170 ti,dp83867-rxctrl-strap-quirk;
171 };
172};
173
174&gpio {
175 status = "okay";
176 gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */
177 "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */
178 "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */
179 "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */
180 "", "", "BUTTON", "LED", "", /* 20 - 24 */
181 "", "PMU_INPUT", "", "", "", /* 25 - 29 */
182 "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */
183 "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */
184 "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */
185 "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */
186 "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */
187 "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */
188 "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */
189 "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */
190 "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */
191 "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */
192 "", "", /* 78 - 79 */
193 "", "", "", "", "", /* 80 - 84 */
194 "", "", "", "", "", /* 85 -89 */
195 "", "", "", "", "", /* 90 - 94 */
196 "", "", "", "", "", /* 95 - 99 */
197 "", "", "", "", "", /* 100 - 104 */
198 "", "", "", "", "", /* 105 - 109 */
199 "", "", "", "", "", /* 110 - 114 */
200 "", "", "", "", "", /* 115 - 119 */
201 "", "", "", "", "", /* 120 - 124 */
202 "", "", "", "", "", /* 125 - 129 */
203 "", "", "", "", "", /* 130 - 134 */
204 "", "", "", "", "", /* 135 - 139 */
205 "", "", "", "", "", /* 140 - 144 */
206 "", "", "", "", "", /* 145 - 149 */
207 "", "", "", "", "", /* 150 - 154 */
208 "", "", "", "", "", /* 155 - 159 */
209 "", "", "", "", "", /* 160 - 164 */
210 "", "", "", "", "", /* 165 - 169 */
211 "", "", "", ""; /* 170 - 174 */
212};
213
214&i2c0 {
215 status = "okay";
216 clock-frequency = <400000>;
217
218 tca6416_u15: gpio@20 { /* u15 */
219 compatible = "ti,tca6416";
220 reg = <0x20>;
221 gpio-controller; /* interrupt not connected */
222 #gpio-cells = <2>;
223 gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */
224 "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */
225 "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */
226 "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */
227 };
228
229 i2c-mux@75 { /* u17 */
230 compatible = "nxp,pca9544";
231 #address-cells = <1>;
232 #size-cells = <0>;
233 reg = <0x75>;
234 i2c@0 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 reg = <0>;
238 /* PS_PMBUS */
239 /* PMBUS_ALERT done via pca9544 */
240 vccint: ina226@40 { /* u65 */
241 compatible = "ti,ina226";
242 #io-channel-cells = <1>;
243 label = "ina226-vccint";
244 reg = <0x40>;
245 shunt-resistor = <5000>;
246 };
247 vccint_io_bram_ps: ina226@41 { /* u57 */
248 compatible = "ti,ina226";
249 #io-channel-cells = <1>;
250 label = "ina226-vccint-io-bram-ps";
251 reg = <0x41>;
252 shunt-resistor = <5000>;
253 };
254 vcc1v8: ina226@42 { /* u60 */
255 compatible = "ti,ina226";
256 #io-channel-cells = <1>;
257 label = "ina226-vcc1v8";
258 reg = <0x42>;
259 shunt-resistor = <2000>;
260 };
261 vcc1v2: ina226@43 { /* u58 */
262 compatible = "ti,ina226";
263 #io-channel-cells = <1>;
264 label = "ina226-vcc1v2";
265 reg = <0x43>;
266 shunt-resistor = <5000>;
267 };
268 vadj_fmc: ina226@45 { /* u62 */
269 compatible = "ti,ina226";
270 #io-channel-cells = <1>;
271 label = "ina226-vadj-fmc";
272 reg = <0x45>;
273 shunt-resistor = <5000>;
274 };
275 mgtavcc: ina226@46 { /* u67 */
276 compatible = "ti,ina226";
277 #io-channel-cells = <1>;
278 label = "ina226-mgtavcc";
279 reg = <0x46>;
280 shunt-resistor = <2000>;
281 };
282 mgt1v2: ina226@47 { /* u63 */
283 compatible = "ti,ina226";
284 #io-channel-cells = <1>;
285 label = "ina226-mgt1v2";
286 reg = <0x47>;
287 shunt-resistor = <5000>;
288 };
289 mgt1v8: ina226@48 { /* u64 */
290 compatible = "ti,ina226";
291 #io-channel-cells = <1>;
292 label = "ina226-mgt1v8";
293 reg = <0x48>;
294 shunt-resistor = <5000>;
295 };
296 vccint_ams: ina226@49 { /* u61 */
297 compatible = "ti,ina226";
298 #io-channel-cells = <1>;
299 label = "ina226-vccint-ams";
300 reg = <0x49>;
301 shunt-resistor = <5000>;
302 };
303 dac_avtt: ina226@4a { /* u59 */
304 compatible = "ti,ina226";
305 #io-channel-cells = <1>;
306 label = "ina226-dac-avtt";
307 reg = <0x4a>;
308 shunt-resistor = <5000>;
309 };
310 dac_avccaux: ina226@4b { /* u124 */
311 compatible = "ti,ina226";
312 #io-channel-cells = <1>;
313 label = "ina226-dac-avccaux";
314 reg = <0x4b>;
315 shunt-resistor = <5000>;
316 };
317 adc_avcc: ina226@4c { /* u75 */
318 compatible = "ti,ina226";
319 #io-channel-cells = <1>;
320 label = "ina226-adc-avcc";
321 reg = <0x4c>;
322 shunt-resistor = <5000>;
323 };
324 adc_avccaux: ina226@4d { /* u71 */
325 compatible = "ti,ina226";
326 #io-channel-cells = <1>;
327 label = "ina226-adc-avccaux";
328 reg = <0x4d>;
329 shunt-resistor = <5000>;
330 };
331 dac_avcc: ina226@4e { /* u77 */
332 compatible = "ti,ina226";
333 #io-channel-cells = <1>;
334 label = "ina226-dac-avcc";
335 reg = <0x4e>;
336 shunt-resistor = <5000>;
337 };
338 };
339 i2c@1 {
340 #address-cells = <1>;
341 #size-cells = <0>;
342 reg = <1>;
343 /* NC */
344 };
345 i2c@2 {
346 #address-cells = <1>;
347 #size-cells = <0>;
348 reg = <2>;
349 /* u104 - ir35215 0x10/0x40 */
350 /* u127 - ir38164 0x1b/0x4b */
351 /* u112 - ir38164 0x13/0x43 */
352 /* u123 - ir38164 0x1c/0x4c */
353
Michal Simek3514e4e2020-03-30 11:35:38 +0200[diff] [blame]354 irps5401_44: irps5401@44 { /* IRPS5401 - u53 */
Michal Simek31e83022019-11-25 08:38:25 +0100[diff] [blame]355 compatible = "infineon,irps5401";
356 reg = <0x44>; /* i2c addr 0x14 */
357 };
Michal Simek3514e4e2020-03-30 11:35:38 +0200[diff] [blame]358 irps5401_45: irps5401@45 { /* IRPS5401 - u55 */
Michal Simek31e83022019-11-25 08:38:25 +0100[diff] [blame]359 compatible = "infineon,irps5401";
360 reg = <0x45>; /* i2c addr 0x15 */
361 };
362 /* J21 header too */
363
364 };
365 i2c@3 {
366 #address-cells = <1>;
367 #size-cells = <0>;
368 reg = <3>;
369 /* SYSMON */
370 };
371 };
372 /* u38 MPS430 */
373};
374
375&i2c1 {
376 status = "okay";
377 clock-frequency = <400000>;
378
379 i2c-mux@74 {
380 compatible = "nxp,pca9548"; /* u20 */
381 #address-cells = <1>;
382 #size-cells = <0>;
383 reg = <0x74>;
384 /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
385 i2c_eeprom: i2c@0 {
386 #address-cells = <1>;
387 #size-cells = <0>;
388 reg = <0>;
389 /*
390 * IIC_EEPROM 1kB memory which uses 256B blocks
391 * where every block has different address.
392 * 0 - 256B address 0x54
393 * 256B - 512B address 0x55
394 * 512B - 768B address 0x56
395 * 768B - 1024B address 0x57
396 */
397 eeprom: eeprom@54 { /* u21 */
398 compatible = "atmel,24c128";
399 reg = <0x54>;
400 };
401 };
402 i2c_si5341: i2c@1 {
403 #address-cells = <1>;
404 #size-cells = <0>;
405 reg = <1>;
406 si5341: clock-generator@36 { /* SI5341 - u43 */
407 compatible = "si5341";
408 reg = <0x36>;
409 };
410
411 };
412 i2c_si570_user_c0: i2c@2 {
413 #address-cells = <1>;
414 #size-cells = <0>;
415 reg = <2>;
416 si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */
417 #clock-cells = <0>;
418 compatible = "silabs,si570";
419 reg = <0x5d>;
420 temperature-stability = <50>;
421 factory-fout = <300000000>;
422 clock-frequency = <300000000>;
423 clock-output-names = "si570_user_c0";
424 };
425 };
426 i2c_si570_mgt: i2c@3 {
427 #address-cells = <1>;
428 #size-cells = <0>;
429 reg = <3>;
430 si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */
431 #clock-cells = <0>;
432 compatible = "silabs,si570";
433 reg = <0x5d>;
434 temperature-stability = <50>;
435 factory-fout = <156250000>;
436 clock-frequency = <148500000>;
437 clock-output-names = "si570_mgt";
438 };
439 };
440 i2c_8a34001: i2c@4 {
441 #address-cells = <1>;
442 #size-cells = <0>;
443 reg = <4>;
Michal Simek1c4e7da2021-01-22 14:42:29 +0100[diff] [blame^]444 idt_8a34001: phc@5b {
445 compatible = "idt,8a34001"; /* u409B */
446 reg = <0x5b>;
447 };
Michal Simek31e83022019-11-25 08:38:25 +0100[diff] [blame]448 };
449 i2c_clk104: i2c@5 {
450 #address-cells = <1>;
451 #size-cells = <0>;
452 reg = <5>;
453 /* CLK104_SDA */
454 };
455 i2c@6 {
456 #address-cells = <1>;
457 #size-cells = <0>;
458 reg = <6>;
459 /* RFMCP connector */
460 };
461 /* 7 NC */
462 };
463
464 i2c-mux@75 {
465 compatible = "nxp,pca9548"; /* u22 */
466 #address-cells = <1>;
467 #size-cells = <0>;
468 reg = <0x75>;
469 /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
470 i2c@0 {
471 #address-cells = <1>;
472 #size-cells = <0>;
473 reg = <0>;
474 /* FMCP_HSPC_IIC */
475 };
476 i2c_si570_user_c1: i2c@1 {
477 #address-cells = <1>;
478 #size-cells = <0>;
479 reg = <1>;
480 si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */
481 #clock-cells = <0>;
482 compatible = "silabs,si570";
483 reg = <0x5d>;
484 temperature-stability = <50>;
485 factory-fout = <300000000>;
486 clock-frequency = <300000000>;
487 clock-output-names = "si570_user_c1";
488 };
489 };
490 i2c@2 {
491 #address-cells = <1>;
492 #size-cells = <0>;
493 reg = <2>;
494 /* SYSMON */
495 };
496 i2c@3 {
497 #address-cells = <1>;
498 #size-cells = <0>;
499 reg = <3>;
500 /* DDR4 SODIMM */
501 };
502 i2c@4 {
503 #address-cells = <1>;
504 #size-cells = <0>;
505 reg = <4>;
506 /* SFP3 */
507 };
508 i2c@5 {
509 #address-cells = <1>;
510 #size-cells = <0>;
511 reg = <5>;
512 /* SFP2 */
513 };
514 i2c@6 {
515 #address-cells = <1>;
516 #size-cells = <0>;
517 reg = <6>;
518 /* SFP1 */
519 };
520 i2c@7 {
521 #address-cells = <1>;
522 #size-cells = <0>;
523 reg = <7>;
524 /* SFP0 */
525 };
526 };
527 /* MSP430 */
528};
529
530&qspi {
531 status = "okay";
532 is-dual = <1>;
533 flash@0 {
534 compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */
535 #address-cells = <1>;
536 #size-cells = <1>;
537 reg = <0>;
538 spi-tx-bus-width = <1>;
539 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
540 spi-max-frequency = <108000000>; /* Based on DC1 spec */
541 };
542};
543
544&rtc {
545 status = "okay";
546};
547
548&sata {
549 status = "okay";
550 /* SATA OOB timing settings */
551 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
552 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
553 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
554 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
555 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
556 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
557 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
558 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
559 phy-names = "sata-phy";
560 phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
561};
562
563/* SD1 with level shifter */
564&sdhci1 {
565 status = "okay";
566 disable-wp;
Manish Naranie2ba0932020-02-13 23:37:30 -0700[diff] [blame]567 /*
568 * This property should be removed for supporting UHS mode
569 */
570 no-1-8-v;
Michal Simek3b662642020-07-22 17:42:43 +0200[diff] [blame]571 xlnx,mio-bank = <1>;
Michal Simek31e83022019-11-25 08:38:25 +0100[diff] [blame]572};
573
574&serdes {
575 status = "okay";
576};
577
578&uart0 {
579 status = "okay";
580};
581
582/* ULPI SMSC USB3320 */
583&usb0 {
584 status = "okay";
585};
586
587&dwc3_0 {
588 status = "okay";
589 dr_mode = "host";
590 snps,usb3_lpm_capable;
591 phy-names = "usb3-phy";
592 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
593};