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git01.mediatek.com / filogic / uboot / 1c41cf066d1e47270b16d144dc202ef60f9fe1d7 / . / arch / arm / dts / imx8mn-ddr4-evk-u-boot.dtsi
blob: 54f3ebe88b8392a706fa0c59ef489134b78e5620 [file] [log] [blame]
Peng Fana181afe2019-09-16 03:09:55 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]3 * Copyright 2019, 2021 NXP
Peng Fana181afe2019-09-16 03:09:55 +0000[diff] [blame]4 */
5
Adam Ford1c41cf02022-10-21 19:58:34 -0500[diff] [blame^]6#include "imx8mn-u-boot.dtsi"
Peng Fana181afe2019-09-16 03:09:55 +0000[diff] [blame]7
8&pinctrl_reg_usdhc2_vmmc {
9 u-boot,dm-spl;
10};
11
Andrey Zhizhikincf51a552020-12-05 17:29:17 +0000[diff] [blame]12&reg_usdhc2_vmmc {
13 u-boot,off-on-delay-us = <20000>;
14};
15
Peng Fana181afe2019-09-16 03:09:55 +0000[diff] [blame]16&pinctrl_uart2 {
17 u-boot,dm-spl;
18};
19
20&pinctrl_usdhc2_gpio {
21 u-boot,dm-spl;
22};
23
24&pinctrl_usdhc2 {
25 u-boot,dm-spl;
26};
27
28&pinctrl_usdhc3 {
29 u-boot,dm-spl;
30};
31
Peng Fan3f9158a2022-05-05 19:05:57 +0800[diff] [blame]32&pinctrl_wdog {
33 u-boot,dm-spl;
34};
35
Peng Fana181afe2019-09-16 03:09:55 +0000[diff] [blame]36&gpio1 {
37 u-boot,dm-spl;
38};
39
40&gpio2 {
41 u-boot,dm-spl;
42};
43
44&gpio3 {
45 u-boot,dm-spl;
46};
47
48&gpio4 {
49 u-boot,dm-spl;
50};
51
52&gpio5 {
53 u-boot,dm-spl;
54};
55
56&uart2 {
57 u-boot,dm-spl;
58};
59
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]60&crypto {
61 u-boot,dm-spl;
62};
63
64&sec_jr0 {
65 u-boot,dm-spl;
66};
67
68&sec_jr1 {
69 u-boot,dm-spl;
70};
71
72&sec_jr2 {
73 u-boot,dm-spl;
74};
75
Peng Fana181afe2019-09-16 03:09:55 +0000[diff] [blame]76&usdhc1 {
77 u-boot,dm-spl;
78};
79
80&usdhc2 {
81 u-boot,dm-spl;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +0000[diff] [blame]82 sd-uhs-sdr104;
83 sd-uhs-ddr50;
Peng Fana181afe2019-09-16 03:09:55 +0000[diff] [blame]84};
85
86&usdhc3 {
87 u-boot,dm-spl;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +0000[diff] [blame]88 mmc-hs400-1_8v;
89 mmc-hs400-enhanced-strobe;
Peng Fana181afe2019-09-16 03:09:55 +0000[diff] [blame]90};