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git01.mediatek.com / filogic / uboot / 1bda3738bf4b126ac36af283ff643ca8cbcdc697 / . / arch / arm / include / asm / arch-omap4 / sys_proto.h
blob: c9f0b3a14b560e897a7e3ae2517d93242a94156d [file] [log] [blame]
Minkyu Kangae6f0c62009-07-20 11:40:01 +0900[diff] [blame]1/*
Steve Sakoman1ad21582010-06-08 13:07:46 -0700[diff] [blame]2 * (C) Copyright 2010
3 * Texas Instruments, <www.ti.com>
Minkyu Kangae6f0c62009-07-20 11:40:01 +0900[diff] [blame]4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Minkyu Kangae6f0c62009-07-20 11:40:01 +0900[diff] [blame]6 */
7
Steve Sakoman1ad21582010-06-08 13:07:46 -0700[diff] [blame]8#ifndef _SYS_PROTO_H_
9#define _SYS_PROTO_H_
10
Sricharan9310ff72011-11-15 09:49:55 -0500[diff] [blame]11#include <asm/arch/omap.h>
Lokesh Vutla61c517f2013-05-30 02:54:32 +0000[diff] [blame]12#include <asm/arch/clock.h>
Steve Sakoman1ad21582010-06-08 13:07:46 -0700[diff] [blame]13#include <asm/io.h>
Aneesh V30679422011-07-21 09:09:59 -0400[diff] [blame]14#include <asm/omap_common.h>
pekon gupta5bbb0992013-11-22 16:53:29 +0530[diff] [blame]15#include <linux/mtd/omap_gpmc.h>
Aneesh Vf908b632011-07-21 09:10:01 -0400[diff] [blame]16#include <asm/arch/mux_omap4.h>
Tom Rini72f36002014-05-16 13:02:24 -0400[diff] [blame]17#include <asm/ti-common/sys_proto.h>
Steve Sakoman1ad21582010-06-08 13:07:46 -0700[diff] [blame]18
SRICHARAN R3f30b0a2013-04-24 00:41:24 +0000[diff] [blame]19DECLARE_GLOBAL_DATA_PTR;
20
Paul Kocialkowski83ec8812016-02-27 19:18:53 +0100[diff] [blame]21#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
Hardik Patel8662fc62013-11-27 21:16:21 +0530[diff] [blame]22extern const struct emif_regs emif_regs_elpida_200_mhz_2cs;
23extern const struct emif_regs emif_regs_elpida_380_mhz_1cs;
24extern const struct emif_regs emif_regs_elpida_400_mhz_1cs;
25extern const struct emif_regs emif_regs_elpida_400_mhz_2cs;
Nishanth Menonc22ced32014-12-18 15:28:35 -0600[diff] [blame]26extern const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2;
27extern const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2;
28extern const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2;
Paul Kocialkowski83ec8812016-02-27 19:18:53 +0100[diff] [blame]29#else
30extern const struct lpddr2_device_details elpida_2G_S4_details;
31extern const struct lpddr2_device_details elpida_4G_S4_details;
32#endif
Paul Kocialkowski6943d342016-02-27 19:18:54 +0100[diff] [blame]33
Paul Kocialkowskiebb7b9f2016-02-27 19:18:55 +0100[diff] [blame]34#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
35extern const struct lpddr2_device_timings jedec_default_timings;
36#else
Paul Kocialkowski6943d342016-02-27 19:18:54 +0100[diff] [blame]37extern const struct lpddr2_device_timings elpida_2G_S4_timings;
38#endif
39
Steve Sakoman1ad21582010-06-08 13:07:46 -0700[diff] [blame]40struct omap_sysinfo {
41 char *board_string;
42};
Aneesh V30679422011-07-21 09:09:59 -0400[diff] [blame]43extern const struct omap_sysinfo sysinfo;
Steve Sakoman1ad21582010-06-08 13:07:46 -0700[diff] [blame]44
Steve Sakoman9b8ea4e2010-07-15 16:19:16 -0400[diff] [blame]45void gpmc_init(void);
Steve Sakoman1ad21582010-06-08 13:07:46 -0700[diff] [blame]46void watchdog_init(void);
47u32 get_device_type(void);
Aneesh Vf908b632011-07-21 09:10:01 -0400[diff] [blame]48void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
Paul Kocialkowskia00b1e52016-02-27 19:18:56 +0100[diff] [blame]49void set_muxconf_regs(void);
Steve Sakoman6e09a762010-08-04 09:39:40 -0700[diff] [blame]50u32 wait_on_value(u32, u32, void *, u32);
51void sdelay(unsigned long);
Kipisz, Stevenebe86dc2016-02-24 12:30:52 -0600[diff] [blame]52void setup_early_clocks(void);
Aneesh V0d2628b2011-07-21 09:10:07 -0400[diff] [blame]53void prcm_init(void);
Kipisz, Steven4466dfb2016-02-24 12:30:57 -0600[diff] [blame]54void do_board_detect(void);
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]55void bypass_dpll(u32 const base);
Aneesh V0d2628b2011-07-21 09:10:07 -0400[diff] [blame]56void freq_update_core(void);
57u32 get_sys_clk_freq(void);
58u32 omap4_ddr_clk(void);
Aneesh Vc0e88522011-07-21 09:10:12 -0400[diff] [blame]59void cancel_out(u32 *num, u32 *den, u32 den_limit);
Aneesh Vcc565582011-07-21 09:10:09 -0400[diff] [blame]60void sdram_init(void);
Sricharan9310ff72011-11-15 09:49:55 -0500[diff] [blame]61u32 omap_sdram_size(void);
62u32 cortex_rev(void);
Tom Rini51df26c2013-05-31 12:31:59 -0400[diff] [blame]63void save_omap_boot_params(void);
Sricharan9310ff72011-11-15 09:49:55 -0500[diff] [blame]64void init_omap_revision(void);
65void do_io_settings(void);
Lokesh Vutlaae49f6d2013-05-30 02:54:33 +0000[diff] [blame]66void sri2c_init(void);
Nishanth Menon41d7ab12012-03-01 14:17:37 +0000[diff] [blame]67int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
Lokesh Vutlae89f1542012-05-29 19:26:41 +0000[diff] [blame]68u32 warm_reset(void);
Lokesh Vutlaba873772012-05-29 19:26:43 +0000[diff] [blame]69void force_emif_self_refresh(void);
Lokesh Vutla100c2d82013-04-17 20:49:40 +0000[diff] [blame]70void setup_warmreset_time(void);
Nishanth Menon19e1fdf2015-03-09 17:12:03 -0500[diff] [blame]71
72#define OMAP4_SERVICE_PL310_CONTROL_REG_SET 0x102
73
Steve Sakoman1ad21582010-06-08 13:07:46 -0700[diff] [blame]74#endif