wdenk | 6ea1cf0 | 2004-02-27 08:20:54 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2004 |
| 3 | * Pierre AUBERT, Staubli Faverges, <p.aubert@staubli.com> |
| 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 6ea1cf0 | 2004-02-27 08:20:54 +0000 | [diff] [blame] | 6 | * |
| 7 | * Init is derived from Linux code. |
| 8 | */ |
| 9 | #include <common.h> |
| 10 | |
Jon Loeliger | 07efe2a | 2007-07-10 10:27:39 -0500 | [diff] [blame] | 11 | #if defined(CONFIG_CMD_IDE) |
wdenk | 6ea1cf0 | 2004-02-27 08:20:54 +0000 | [diff] [blame] | 12 | #include <mpc5xxx.h> |
| 13 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 14 | DECLARE_GLOBAL_DATA_PTR; |
| 15 | |
wdenk | 6ea1cf0 | 2004-02-27 08:20:54 +0000 | [diff] [blame] | 16 | #define CALC_TIMING(t) (t + period - 1) / period |
| 17 | |
wdenk | acd9b10 | 2004-03-14 00:59:59 +0000 | [diff] [blame] | 18 | #ifdef CONFIG_IDE_RESET |
| 19 | extern void init_ide_reset (void); |
| 20 | #endif |
wdenk | 6ea1cf0 | 2004-02-27 08:20:54 +0000 | [diff] [blame] | 21 | |
| 22 | int ide_preinit (void) |
| 23 | { |
wdenk | 6ea1cf0 | 2004-02-27 08:20:54 +0000 | [diff] [blame] | 24 | long period, t0, t1, t2_8, t2_16, t4, ta; |
| 25 | vu_long reg; |
| 26 | struct mpc5xxx_sdma *psdma = (struct mpc5xxx_sdma *) MPC5XXX_SDMA; |
| 27 | |
| 28 | reg = *(vu_long *) MPC5XXX_GPS_PORT_CONFIG; |
Grzegorz Bernacki | 81e8199 | 2009-03-17 10:06:39 +0100 | [diff] [blame] | 29 | #if defined(CONFIG_SYS_ATA_CS_ON_I2C2) |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 30 | /* ATA cs0/1 on i2c2 clk/io */ |
| 31 | reg = (reg & ~0x03000000ul) | 0x02000000ul; |
Jon Smirl | bc03df9 | 2009-06-14 18:21:28 -0400 | [diff] [blame] | 32 | #elif defined(CONFIG_SYS_ATA_CS_ON_TIMER01) |
| 33 | /* ATA cs0/1 on Timer 0/1 */ |
| 34 | reg = (reg & ~0x03000000ul) | 0x03000000ul; |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 35 | #else |
| 36 | /* ATA cs0/1 on Local Plus cs4/5 */ |
wdenk | 6ea1cf0 | 2004-02-27 08:20:54 +0000 | [diff] [blame] | 37 | reg = (reg & ~0x03000000ul) | 0x01000000ul; |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 38 | #endif /* CONFIG_TOTAL5200 */ |
wdenk | 6ea1cf0 | 2004-02-27 08:20:54 +0000 | [diff] [blame] | 39 | *(vu_long *) MPC5XXX_GPS_PORT_CONFIG = reg; |
| 40 | |
| 41 | /* All sample codes do that... */ |
| 42 | *(vu_long *) MPC5XXX_ATA_SHARE_COUNT = 0; |
| 43 | |
Heiko Schocher | 991d701 | 2007-08-28 17:40:33 +0200 | [diff] [blame] | 44 | #if defined(CONFIG_UC101) |
| 45 | /* Configure and reset host */ |
Wolfgang Denk | ec8b22b | 2007-08-29 01:32:05 +0200 | [diff] [blame] | 46 | *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = |
Heiko Schocher | 991d701 | 2007-08-28 17:40:33 +0200 | [diff] [blame] | 47 | MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR; |
| 48 | udelay (10); |
| 49 | *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = 0; |
| 50 | #else |
wdenk | 6ea1cf0 | 2004-02-27 08:20:54 +0000 | [diff] [blame] | 51 | /* Configure and reset host */ |
| 52 | *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY | |
| 53 | MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR; |
| 54 | udelay (10); |
| 55 | *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY; |
Heiko Schocher | 991d701 | 2007-08-28 17:40:33 +0200 | [diff] [blame] | 56 | #endif |
wdenk | 6ea1cf0 | 2004-02-27 08:20:54 +0000 | [diff] [blame] | 57 | |
| 58 | /* Disable prefetch on Commbus */ |
| 59 | psdma->PtdCntrl |= 1; |
| 60 | |
| 61 | /* Init timings : we use PIO mode 0 timings */ |
Simon Glass | 4f8c5f0 | 2012-12-13 20:48:53 +0000 | [diff] [blame] | 62 | period = 1000000000 / gd->arch.ipb_clk; /* period in ns */ |
wdenk | 6ea1cf0 | 2004-02-27 08:20:54 +0000 | [diff] [blame] | 63 | |
| 64 | t0 = CALC_TIMING (600); |
| 65 | t2_8 = CALC_TIMING (290); |
| 66 | t2_16 = CALC_TIMING (165); |
| 67 | reg = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8); |
| 68 | *(vu_long *) MPC5XXX_ATA_PIO1 = reg; |
| 69 | |
| 70 | t4 = CALC_TIMING (30); |
| 71 | t1 = CALC_TIMING (70); |
| 72 | ta = CALC_TIMING (35); |
| 73 | reg = (t4 << 24) | (t1 << 16) | (ta << 8); |
| 74 | |
| 75 | *(vu_long *) MPC5XXX_ATA_PIO2 = reg; |
| 76 | |
wdenk | acd9b10 | 2004-03-14 00:59:59 +0000 | [diff] [blame] | 77 | #ifdef CONFIG_IDE_RESET |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 78 | init_ide_reset (); |
wdenk | acd9b10 | 2004-03-14 00:59:59 +0000 | [diff] [blame] | 79 | #endif /* CONFIG_IDE_RESET */ |
wdenk | 6ea1cf0 | 2004-02-27 08:20:54 +0000 | [diff] [blame] | 80 | |
| 81 | return (0); |
| 82 | } |
Jon Loeliger | 07efe2a | 2007-07-10 10:27:39 -0500 | [diff] [blame] | 83 | #endif |