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wdenk6ea1cf02004-02-27 08:20:54 +00001/*
2 * (C) Copyright 2004
3 * Pierre AUBERT, Staubli Faverges, <p.aubert@staubli.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk6ea1cf02004-02-27 08:20:54 +00006 *
7 * Init is derived from Linux code.
8 */
9#include <common.h>
10
Jon Loeliger07efe2a2007-07-10 10:27:39 -050011#if defined(CONFIG_CMD_IDE)
wdenk6ea1cf02004-02-27 08:20:54 +000012#include <mpc5xxx.h>
13
Wolfgang Denk6405a152006-03-31 18:32:53 +020014DECLARE_GLOBAL_DATA_PTR;
15
wdenk6ea1cf02004-02-27 08:20:54 +000016#define CALC_TIMING(t) (t + period - 1) / period
17
wdenkacd9b102004-03-14 00:59:59 +000018#ifdef CONFIG_IDE_RESET
19extern void init_ide_reset (void);
20#endif
wdenk6ea1cf02004-02-27 08:20:54 +000021
22int ide_preinit (void)
23{
wdenk6ea1cf02004-02-27 08:20:54 +000024 long period, t0, t1, t2_8, t2_16, t4, ta;
25 vu_long reg;
26 struct mpc5xxx_sdma *psdma = (struct mpc5xxx_sdma *) MPC5XXX_SDMA;
27
28 reg = *(vu_long *) MPC5XXX_GPS_PORT_CONFIG;
Grzegorz Bernacki81e81992009-03-17 10:06:39 +010029#if defined(CONFIG_SYS_ATA_CS_ON_I2C2)
wdenkcc3f8a92004-07-11 19:17:20 +000030 /* ATA cs0/1 on i2c2 clk/io */
31 reg = (reg & ~0x03000000ul) | 0x02000000ul;
Jon Smirlbc03df92009-06-14 18:21:28 -040032#elif defined(CONFIG_SYS_ATA_CS_ON_TIMER01)
33 /* ATA cs0/1 on Timer 0/1 */
34 reg = (reg & ~0x03000000ul) | 0x03000000ul;
wdenkcc3f8a92004-07-11 19:17:20 +000035#else
36 /* ATA cs0/1 on Local Plus cs4/5 */
wdenk6ea1cf02004-02-27 08:20:54 +000037 reg = (reg & ~0x03000000ul) | 0x01000000ul;
wdenkcc3f8a92004-07-11 19:17:20 +000038#endif /* CONFIG_TOTAL5200 */
wdenk6ea1cf02004-02-27 08:20:54 +000039 *(vu_long *) MPC5XXX_GPS_PORT_CONFIG = reg;
40
41 /* All sample codes do that... */
42 *(vu_long *) MPC5XXX_ATA_SHARE_COUNT = 0;
43
Heiko Schocher991d7012007-08-28 17:40:33 +020044#if defined(CONFIG_UC101)
45 /* Configure and reset host */
Wolfgang Denkec8b22b2007-08-29 01:32:05 +020046 *(vu_long *) MPC5XXX_ATA_HOST_CONFIG =
Heiko Schocher991d7012007-08-28 17:40:33 +020047 MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR;
48 udelay (10);
49 *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = 0;
50#else
wdenk6ea1cf02004-02-27 08:20:54 +000051 /* Configure and reset host */
52 *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY |
53 MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR;
54 udelay (10);
55 *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY;
Heiko Schocher991d7012007-08-28 17:40:33 +020056#endif
wdenk6ea1cf02004-02-27 08:20:54 +000057
58 /* Disable prefetch on Commbus */
59 psdma->PtdCntrl |= 1;
60
61 /* Init timings : we use PIO mode 0 timings */
Simon Glass4f8c5f02012-12-13 20:48:53 +000062 period = 1000000000 / gd->arch.ipb_clk; /* period in ns */
wdenk6ea1cf02004-02-27 08:20:54 +000063
64 t0 = CALC_TIMING (600);
65 t2_8 = CALC_TIMING (290);
66 t2_16 = CALC_TIMING (165);
67 reg = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8);
68 *(vu_long *) MPC5XXX_ATA_PIO1 = reg;
69
70 t4 = CALC_TIMING (30);
71 t1 = CALC_TIMING (70);
72 ta = CALC_TIMING (35);
73 reg = (t4 << 24) | (t1 << 16) | (ta << 8);
74
75 *(vu_long *) MPC5XXX_ATA_PIO2 = reg;
76
wdenkacd9b102004-03-14 00:59:59 +000077#ifdef CONFIG_IDE_RESET
wdenkc35ba4e2004-03-14 22:25:36 +000078 init_ide_reset ();
wdenkacd9b102004-03-14 00:59:59 +000079#endif /* CONFIG_IDE_RESET */
wdenk6ea1cf02004-02-27 08:20:54 +000080
81 return (0);
82}
Jon Loeliger07efe2a2007-07-10 10:27:39 -050083#endif