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git01.mediatek.com / filogic / uboot / 1ba1d4eb222ae1712865949057912c2f7785543f / . / arch / arm / dts / k3-am65-wakeup.dtsi
blob: ed42f13e7663479bbeefeb87d5d3817fc40782c8 [file] [log] [blame]
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM6 SoC Family Wakeup Domain peripherals
4 *
Lokesh Vutla462275c2021-02-01 11:26:39 +0530[diff] [blame]5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]6 */
7
8&cbass_wakeup {
9 dmsc: dmsc {
Grygorii Strashkod64c5b22019-02-05 17:31:21 +0530[diff] [blame]10 compatible = "ti,am654-sci";
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]11 ti,host-id = <12>;
12 #address-cells = <1>;
13 #size-cells = <1>;
14 ranges;
15
16 mbox-names = "rx", "tx";
17
18 mboxes= <&secure_proxy_main 11>,
19 <&secure_proxy_main 13>;
20
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
Lokesh Vutla61ff6a32019-06-07 19:24:47 +0530[diff] [blame]23 #power-domain-cells = <2>;
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]24 };
25
26 k3_clks: clocks {
27 compatible = "ti,k2g-sci-clk";
28 #clock-cells = <2>;
29 };
30
31 k3_reset: reset-controller {
32 compatible = "ti,sci-reset";
33 #reset-cells = <2>;
34 };
35 };
36
Lokesh Vutla462275c2021-02-01 11:26:39 +0530[diff] [blame]37 chipid@43000014 {
38 compatible = "ti,am654-chipid";
39 reg = <0x43000014 0x4>;
40 };
41
42 wkup_pmx0: pinctrl@4301c000 {
Andreas Dannenberg9976b862019-06-04 18:08:13 -0500[diff] [blame]43 compatible = "pinctrl-single";
44 reg = <0x4301c000 0x118>;
45 #pinctrl-cells = <1>;
46 pinctrl-single,register-width = <32>;
47 pinctrl-single,function-mask = <0xffffffff>;
48 };
49
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]50 wkup_uart0: serial@42300000 {
51 compatible = "ti,am654-uart";
52 reg = <0x42300000 0x100>;
53 reg-shift = <2>;
54 reg-io-width = <4>;
55 interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
56 clock-frequency = <48000000>;
57 current-speed = <115200>;
Lokesh Vutla462275c2021-02-01 11:26:39 +0530[diff] [blame]58 power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]59 };
Andreas Dannenberge3179be2019-06-04 18:08:14 -0500[diff] [blame]60
61 wkup_i2c0: i2c@42120000 {
62 compatible = "ti,am654-i2c", "ti,omap4-i2c";
63 reg = <0x42120000 0x100>;
64 interrupts = <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
65 #address-cells = <1>;
66 #size-cells = <0>;
67 clock-names = "fck";
68 clocks = <&k3_clks 115 1>;
Lokesh Vutla61ff6a32019-06-07 19:24:47 +0530[diff] [blame]69 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
Andreas Dannenberge3179be2019-06-04 18:08:14 -0500[diff] [blame]70 };
Dave Gerlachc70c4962020-07-15 23:40:00 -0500[diff] [blame]71
Lokesh Vutla462275c2021-02-01 11:26:39 +0530[diff] [blame]72 intr_wkup_gpio: interrupt-controller2 {
73 compatible = "ti,sci-intr";
74 ti,intr-trigger-type = <1>;
75 interrupt-controller;
76 interrupt-parent = <&gic500>;
77 #interrupt-cells = <1>;
78 ti,sci = <&dmsc>;
79 ti,sci-dev-id = <156>;
80 ti,interrupt-ranges = <0 712 16>;
81 };
82
83 wkup_gpio0: gpio@42110000 {
84 compatible = "ti,am654-gpio", "ti,keystone-gpio";
85 reg = <0x42110000 0x100>;
86 gpio-controller;
87 #gpio-cells = <2>;
88 interrupt-parent = <&intr_wkup_gpio>;
89 interrupts = <60>, <61>, <62>, <63>;
90 interrupt-controller;
91 #interrupt-cells = <2>;
92 ti,ngpio = <56>;
93 ti,davinci-gpio-unbanked = <0>;
94 clocks = <&k3_clks 59 0>;
95 clock-names = "gpio";
96 };
97
98 wkup_vtm0: temperature-sensor@42050000 {
99 compatible = "ti,am654-vtm";
100 reg = <0x42050000 0x25c>;
101 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
102 #thermal-sensor-cells = <1>;
103 };
104
105 thermal_zones: thermal-zones {
106 #include "k3-am654-industrial-thermal.dtsi"
Dave Gerlachc70c4962020-07-15 23:40:00 -0500[diff] [blame]107 };
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]108};