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git01.mediatek.com / filogic / uboot / 1b8d41c66ce3985e3a53e1f118b6e655a05e8197 / . / drivers / clk / renesas / r8a779h0-cpg-mssr.c
blob: 2e98e262fb0ede3af60555f5b16dc6d8244242c7 [file] [log] [blame]
Hai Pham28028692024-01-28 16:52:01 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * r8a779h0 Clock Pulse Generator / Module Standby and Software Reset
4 *
5 * Copyright (C) 2023 Renesas Electronics Corp.
6 *
7 * Based on r8a779g0-cpg-mssr.c
8 */
9
10#include <clk-uclass.h>
11#include <dm.h>
12
13#include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h>
14
15#include "renesas-cpg-mssr.h"
16#include "rcar-gen3-cpg.h"
17
Marek Vasutb6cc9842024-09-13 01:53:59 +0200[diff] [blame]18#define CPG_SD0CKCR 0x870 /* SD-IF0 Clock Frequency Control Register */
19#define CPG_CANFDCKCR 0x878 /* CAN-FD Clock Frequency Control Register */
20#define CPG_MSOCKCR 0x87c /* MSIOF Clock Frequency Control Register */
21#define CPG_CSICKCR 0x880 /* CSI Clock Frequency Control Register */
22#define CPG_DSIEXTCKCR 0x884 /* DSI Clock Frequency Control Register */
23
Hai Pham28028692024-01-28 16:52:01 +0100[diff] [blame]24enum clk_ids {
25 /* Core Clock Outputs exported to DT */
26 LAST_DT_CORE_CLK = R8A779H0_CLK_R,
27
28 /* External Input Clocks */
29 CLK_EXTAL,
30 CLK_EXTALR,
31
32 /* Internal Core Clocks */
33 CLK_MAIN,
34 CLK_PLL1,
35 CLK_PLL2,
36 CLK_PLL3,
37 CLK_PLL4,
38 CLK_PLL5,
39 CLK_PLL6,
40 CLK_PLL7,
41 CLK_PLL1_DIV2,
42 CLK_PLL2_DIV2,
43 CLK_PLL3_DIV2,
44 CLK_PLL4_DIV2,
45 CLK_PLL4_DIV5,
46 CLK_PLL5_DIV2,
47 CLK_PLL5_DIV4,
48 CLK_PLL6_DIV2,
49 CLK_PLL7_DIV2,
50 CLK_S0,
51 CLK_S0_VIO,
52 CLK_S0_VC,
53 CLK_S0_HSC,
54 CLK_SASYNCPER,
55 CLK_SV_VIP,
56 CLK_SV_IR,
57 CLK_IMPASRC,
58 CLK_IMPBSRC,
59 CLK_VIOSRC,
60 CLK_VCSRC,
61 CLK_SDSRC,
62 CLK_RPCSRC,
63 CLK_OCO,
64
65 /* Module Clocks */
66 MOD_CLK_BASE
67};
68
69static const struct cpg_core_clk r8a779h0_core_clks[] = {
70 /* External Clock Inputs */
71 DEF_INPUT("extal", CLK_EXTAL),
72 DEF_INPUT("extalr", CLK_EXTALR),
73
74 /* Internal Core Clocks */
75 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
76 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
77 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN),
78 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
79 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN),
80 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
81 DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
82 DEF_BASE(".pll7", CLK_PLL7, CLK_TYPE_GEN4_PLL7, CLK_MAIN),
83
84 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
85 DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1),
86 DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1),
87 DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1),
88 DEF_FIXED(".pll4_div5", CLK_PLL4_DIV5, CLK_PLL4, 5, 1),
89 DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
90 DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
91 DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1),
92 DEF_FIXED(".pll7_div2", CLK_PLL7_DIV2, CLK_PLL7, 2, 1),
93 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
94 DEF_FIXED(".s0_vio", CLK_S0_VIO, CLK_PLL1_DIV2, 2, 1),
95 DEF_FIXED(".s0_vc", CLK_S0_VC, CLK_PLL1_DIV2, 2, 1),
96 DEF_FIXED(".s0_hsc", CLK_S0_HSC, CLK_PLL1_DIV2, 2, 1),
97 DEF_FIXED(".sasyncper", CLK_SASYNCPER, CLK_PLL5_DIV4, 3, 1),
98 DEF_FIXED(".sv_vip", CLK_SV_VIP, CLK_PLL1, 5, 1),
99 DEF_FIXED(".sv_ir", CLK_SV_IR, CLK_PLL1, 5, 1),
100 DEF_FIXED(".impasrc", CLK_IMPASRC, CLK_PLL1_DIV2, 2, 1),
101 DEF_FIXED(".impbsrc", CLK_IMPBSRC, CLK_PLL1, 4, 1),
102 DEF_FIXED(".viosrc", CLK_VIOSRC, CLK_PLL1, 6, 1),
103 DEF_FIXED(".vcsrc", CLK_VCSRC, CLK_PLL1, 6, 1),
104 DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
105 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
106 DEF_RATE(".oco", CLK_OCO, 32768),
107
108 /* Core Clock Outputs */
109 DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 0),
110 DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 8),
111 DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 32),
112 DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 40),
113 DEF_FIXED("s0d2", R8A779H0_CLK_S0D2, CLK_S0, 2, 1),
114 DEF_FIXED("s0d3", R8A779H0_CLK_S0D3, CLK_S0, 3, 1),
115 DEF_FIXED("s0d4", R8A779H0_CLK_S0D4, CLK_S0, 4, 1),
116 DEF_FIXED("cl16m", R8A779H0_CLK_CL16M, CLK_S0, 48, 1),
117 DEF_FIXED("s0d2_rt", R8A779H0_CLK_S0D2_RT, CLK_S0, 2, 1),
118 DEF_FIXED("s0d3_rt", R8A779H0_CLK_S0D3_RT, CLK_S0, 3, 1),
119 DEF_FIXED("s0d4_rt", R8A779H0_CLK_S0D4_RT, CLK_S0, 4, 1),
120 DEF_FIXED("s0d6_rt", R8A779H0_CLK_S0D6_RT, CLK_S0, 6, 1),
121 DEF_FIXED("cl16m_rt", R8A779H0_CLK_CL16M_RT, CLK_S0, 48, 1),
122 DEF_FIXED("s0d2_per", R8A779H0_CLK_S0D2_PER, CLK_S0, 2, 1),
123 DEF_FIXED("s0d3_per", R8A779H0_CLK_S0D3_PER, CLK_S0, 3, 1),
124 DEF_FIXED("s0d4_per", R8A779H0_CLK_S0D4_PER, CLK_S0, 4, 1),
125 DEF_FIXED("s0d6_per", R8A779H0_CLK_S0D6_PER, CLK_S0, 6, 1),
126 DEF_FIXED("s0d12_per", R8A779H0_CLK_S0D12_PER, CLK_S0, 12, 1),
127 DEF_FIXED("s0d24_per", R8A779H0_CLK_S0D24_PER, CLK_S0, 24, 1),
128 DEF_FIXED("cl16m_per", R8A779H0_CLK_CL16M_PER, CLK_S0, 48, 1),
129 DEF_FIXED("s0d2_mm", R8A779H0_CLK_S0D2_MM, CLK_S0, 2, 1),
130 DEF_FIXED("s0d4_mm", R8A779H0_CLK_S0D4_MM, CLK_S0, 4, 1),
131 DEF_FIXED("cl16m_mm", R8A779H0_CLK_CL16M_MM, CLK_S0, 48, 1),
132 DEF_FIXED("s0d2_u3dg", R8A779H0_CLK_S0D2_U3DG, CLK_S0, 2, 1),
133 DEF_FIXED("s0d4_u3dg", R8A779H0_CLK_S0D4_U3DG, CLK_S0, 4, 1),
134 DEF_FIXED("s0d1_vio", R8A779H0_CLK_S0D1_VIO, CLK_S0_VIO, 1, 1),
135 DEF_FIXED("s0d2_vio", R8A779H0_CLK_S0D2_VIO, CLK_S0_VIO, 2, 1),
136 DEF_FIXED("s0d4_vio", R8A779H0_CLK_S0D4_VIO, CLK_S0_VIO, 4, 1),
137 DEF_FIXED("s0d8_vio", R8A779H0_CLK_S0D8_VIO, CLK_S0_VIO, 8, 1),
138 DEF_FIXED("s0d1_vc", R8A779H0_CLK_S0D1_VC, CLK_S0_VC, 1, 1),
139 DEF_FIXED("s0d2_vc", R8A779H0_CLK_S0D2_VC, CLK_S0_VC, 2, 1),
140 DEF_FIXED("s0d4_vc", R8A779H0_CLK_S0D4_VC, CLK_S0_VC, 4, 1),
141 DEF_FIXED("s0d1_hsc", R8A779H0_CLK_S0D1_HSC, CLK_S0_HSC, 1, 1),
142 DEF_FIXED("s0d2_hsc", R8A779H0_CLK_S0D2_HSC, CLK_S0_HSC, 2, 1),
143 DEF_FIXED("s0d4_hsc", R8A779H0_CLK_S0D4_HSC, CLK_S0_HSC, 4, 1),
144 DEF_FIXED("s0d8_hsc", R8A779H0_CLK_S0D8_HSC, CLK_S0_HSC, 8, 1),
145 DEF_FIXED("cl16m_hsc", R8A779H0_CLK_CL16M_HSC, CLK_S0_HSC, 48, 1),
146 DEF_FIXED("sasyncrt", R8A779H0_CLK_SASYNCRT, CLK_PLL5_DIV4, 48, 1),
147 DEF_FIXED("sasyncperd1", R8A779H0_CLK_SASYNCPERD1, CLK_SASYNCPER, 1, 1),
148 DEF_FIXED("sasyncperd2", R8A779H0_CLK_SASYNCPERD2, CLK_SASYNCPER, 2, 1),
149 DEF_FIXED("sasyncperd4", R8A779H0_CLK_SASYNCPERD4, CLK_SASYNCPER, 4, 1),
150 DEF_FIXED("svd1_vip", R8A779H0_CLK_SVD1_VIP, CLK_SV_VIP, 1, 1),
151 DEF_FIXED("svd2_vip", R8A779H0_CLK_SVD2_VIP, CLK_SV_VIP, 2, 1),
152 DEF_FIXED("svd1_ir", R8A779H0_CLK_SVD1_IR, CLK_SV_IR, 1, 1),
153 DEF_FIXED("svd2_ir", R8A779H0_CLK_SVD2_IR, CLK_SV_IR, 2, 1),
154 DEF_FIXED("cbfusa", R8A779H0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
155 DEF_FIXED("cpex", R8A779H0_CLK_CPEX, CLK_EXTAL, 2, 1),
156 DEF_FIXED("cp", R8A779H0_CLK_CP, CLK_EXTAL, 2, 1),
157 DEF_FIXED("impad1", R8A779H0_CLK_IMPAD1, CLK_IMPASRC, 1, 1),
158 DEF_FIXED("impad4", R8A779H0_CLK_IMPAD4, CLK_IMPASRC, 4, 1),
159 DEF_FIXED("impb", R8A779H0_CLK_IMPB, CLK_IMPBSRC, 1, 1),
160 DEF_FIXED("viobusd1", R8A779H0_CLK_VIOBUSD1, CLK_VIOSRC, 1, 1),
161 DEF_FIXED("viobusd2", R8A779H0_CLK_VIOBUSD2, CLK_VIOSRC, 2, 1),
162 DEF_FIXED("vcbusd1", R8A779H0_CLK_VCBUSD1, CLK_VCSRC, 1, 1),
163 DEF_FIXED("vcbusd2", R8A779H0_CLK_VCBUSD2, CLK_VCSRC, 2, 1),
Marek Vasutb6cc9842024-09-13 01:53:59 +0200[diff] [blame]164 DEF_DIV6P1("canfd", R8A779H0_CLK_CANFD, CLK_PLL5_DIV4, CPG_CANFDCKCR),
165 DEF_DIV6P1("csi", R8A779H0_CLK_CSI, CLK_PLL5_DIV4, CPG_CSICKCR),
Hai Pham28028692024-01-28 16:52:01 +0100[diff] [blame]166 DEF_FIXED("dsiref", R8A779H0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1),
Marek Vasutb6cc9842024-09-13 01:53:59 +0200[diff] [blame]167 DEF_DIV6P1("dsiext", R8A779H0_CLK_DSIEXT, CLK_PLL5_DIV4, CPG_DSIEXTCKCR),
168 DEF_DIV6P1("mso", R8A779H0_CLK_MSO, CLK_PLL5_DIV4, CPG_MSOCKCR),
Hai Pham28028692024-01-28 16:52:01 +0100[diff] [blame]169
Marek Vasutb6cc9842024-09-13 01:53:59 +0200[diff] [blame]170 DEF_GEN4_SDH("sd0h", R8A779H0_CLK_SD0H, CLK_SDSRC, CPG_SD0CKCR),
171 DEF_GEN4_SD("sd0", R8A779H0_CLK_SD0, R8A779H0_CLK_SD0H, CPG_SD0CKCR),
Hai Pham28028692024-01-28 16:52:01 +0100[diff] [blame]172
173 DEF_BASE("rpc", R8A779H0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
174 DEF_BASE("rpcd2", R8A779H0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779H0_CLK_RPC),
175
176 DEF_GEN4_OSC("osc", R8A779H0_CLK_OSC, CLK_EXTAL, 8),
177 DEF_GEN4_MDSEL("r", R8A779H0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
178};
179
180static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
Marek Vasut8311c392024-06-19 00:54:19 +0200[diff] [blame]181 DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC),
182 DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC),
183 DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC),
Marek Vasutb6cc9842024-09-13 01:53:59 +0200[diff] [blame]184 DEF_MOD("canfd0", 328, R8A779H0_CLK_SASYNCPERD2),
185 DEF_MOD("csi40", 331, R8A779H0_CLK_CSI),
186 DEF_MOD("csi41", 400, R8A779H0_CLK_CSI),
Hai Pham28028692024-01-28 16:52:01 +0100[diff] [blame]187 DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1),
188 DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1),
189 DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1),
190 DEF_MOD("hscif3", 517, R8A779H0_CLK_SASYNCPERD1),
191 DEF_MOD("i2c0", 518, R8A779H0_CLK_S0D6_PER),
192 DEF_MOD("i2c1", 519, R8A779H0_CLK_S0D6_PER),
193 DEF_MOD("i2c2", 520, R8A779H0_CLK_S0D6_PER),
194 DEF_MOD("i2c3", 521, R8A779H0_CLK_S0D6_PER),
Marek Vasutb6cc9842024-09-13 01:53:59 +0200[diff] [blame]195 DEF_MOD("irqc", 611, R8A779H0_CLK_CL16M),
196 DEF_MOD("ispcs0", 612, R8A779H0_CLK_S0D2_VIO),
197 DEF_MOD("ispcs1", 613, R8A779H0_CLK_S0D2_VIO),
198 DEF_MOD("msi0", 618, R8A779H0_CLK_MSO),
199 DEF_MOD("msi1", 619, R8A779H0_CLK_MSO),
200 DEF_MOD("msi2", 620, R8A779H0_CLK_MSO),
201 DEF_MOD("msi3", 621, R8A779H0_CLK_MSO),
202 DEF_MOD("msi4", 622, R8A779H0_CLK_MSO),
203 DEF_MOD("msi5", 623, R8A779H0_CLK_MSO),
204 DEF_MOD("pcie0", 624, R8A779H0_CLK_S0D2_HSC),
205 DEF_MOD("pwm", 628, R8A779H0_CLK_SASYNCPERD4),
Hai Pham28028692024-01-28 16:52:01 +0100[diff] [blame]206 DEF_MOD("rpc-if", 629, R8A779H0_CLK_RPCD2),
Marek Vasutb6cc9842024-09-13 01:53:59 +0200[diff] [blame]207 DEF_MOD("scif0", 702, R8A779H0_CLK_SASYNCPERD4),
208 DEF_MOD("scif1", 703, R8A779H0_CLK_SASYNCPERD4),
209 DEF_MOD("scif3", 704, R8A779H0_CLK_SASYNCPERD4),
210 DEF_MOD("scif4", 705, R8A779H0_CLK_SASYNCPERD4),
Hai Pham28028692024-01-28 16:52:01 +0100[diff] [blame]211 DEF_MOD("sdhi0", 706, R8A779H0_CLK_SD0),
Marek Vasut8311c392024-06-19 00:54:19 +0200[diff] [blame]212 DEF_MOD("sydm1", 709, R8A779H0_CLK_S0D6_PER),
213 DEF_MOD("sydm2", 710, R8A779H0_CLK_S0D6_PER),
Marek Vasutb6cc9842024-09-13 01:53:59 +0200[diff] [blame]214 DEF_MOD("tmu0", 713, R8A779H0_CLK_SASYNCRT),
215 DEF_MOD("tmu1", 714, R8A779H0_CLK_SASYNCPERD2),
216 DEF_MOD("tmu2", 715, R8A779H0_CLK_SASYNCPERD2),
217 DEF_MOD("tmu3", 716, R8A779H0_CLK_SASYNCPERD2),
218 DEF_MOD("tmu4", 717, R8A779H0_CLK_SASYNCPERD2),
219 DEF_MOD("vin00", 730, R8A779H0_CLK_S0D4_VIO),
220 DEF_MOD("vin01", 731, R8A779H0_CLK_S0D4_VIO),
221 DEF_MOD("vin02", 800, R8A779H0_CLK_S0D4_VIO),
222 DEF_MOD("vin03", 801, R8A779H0_CLK_S0D4_VIO),
223 DEF_MOD("vin04", 802, R8A779H0_CLK_S0D4_VIO),
224 DEF_MOD("vin05", 803, R8A779H0_CLK_S0D4_VIO),
225 DEF_MOD("vin06", 804, R8A779H0_CLK_S0D4_VIO),
226 DEF_MOD("vin07", 805, R8A779H0_CLK_S0D4_VIO),
227 DEF_MOD("vin10", 806, R8A779H0_CLK_S0D4_VIO),
228 DEF_MOD("vin11", 807, R8A779H0_CLK_S0D4_VIO),
229 DEF_MOD("vin12", 808, R8A779H0_CLK_S0D4_VIO),
230 DEF_MOD("vin13", 809, R8A779H0_CLK_S0D4_VIO),
231 DEF_MOD("vin14", 810, R8A779H0_CLK_S0D4_VIO),
232 DEF_MOD("vin15", 811, R8A779H0_CLK_S0D4_VIO),
233 DEF_MOD("vin16", 812, R8A779H0_CLK_S0D4_VIO),
234 DEF_MOD("vin17", 813, R8A779H0_CLK_S0D4_VIO),
Marek Vasut8311c392024-06-19 00:54:19 +0200[diff] [blame]235 DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R),
Marek Vasutb6cc9842024-09-13 01:53:59 +0200[diff] [blame]236 DEF_MOD("cmt0", 910, R8A779H0_CLK_R),
237 DEF_MOD("cmt1", 911, R8A779H0_CLK_R),
238 DEF_MOD("cmt2", 912, R8A779H0_CLK_R),
239 DEF_MOD("cmt3", 913, R8A779H0_CLK_R),
Marek Vasut8311c392024-06-19 00:54:19 +0200[diff] [blame]240 DEF_MOD("pfc0", 915, R8A779H0_CLK_CP),
241 DEF_MOD("pfc1", 916, R8A779H0_CLK_CP),
242 DEF_MOD("pfc2", 917, R8A779H0_CLK_CP),
Marek Vasutb6cc9842024-09-13 01:53:59 +0200[diff] [blame]243 DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M),
244 DEF_MOD("ssiu", 2926, R8A779H0_CLK_S0D6_PER),
245 DEF_MOD("ssi", 2927, R8A779H0_CLK_S0D6_PER),
Hai Pham28028692024-01-28 16:52:01 +0100[diff] [blame]246};
247
248/*
249 * CPG Clock Data
250 */
251/*
252 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
253 * 14 13 (MHz)
254 * ------------------------------------------------------------------------
255 * 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /16
256 * 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19
257 * 1 0 Prohibited setting
258 * 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /32
259 */
260#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
261 (((md) & BIT(13)) >> 13))
262
263static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
Marek Vasut55f08262024-01-28 16:52:02 +0100[diff] [blame]264 /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv PLL7 mult/div */
265 { 1, 192, 1, 240, 1, 192, 1, 240, 1, 192, 1, 168, 1, 16, 120, 1, },
266 { 1, 160, 1, 200, 1, 160, 1, 200, 1, 160, 1, 140, 1, 19, 100, 1, },
267 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
268 { 2, 192, 1, 240, 1, 192, 1, 240, 1, 192, 1, 168, 1, 32, 120, 1, },
Hai Pham28028692024-01-28 16:52:01 +0100[diff] [blame]269};
270
271/*
272 * Note that the only clock left running before booting Linux are now
273 * MFIS, INTC-AP, INTC-EX, SCIF0, HSCIF0 on V4M
274 */
275#define MSTPCR5_INTCAP BIT(11)
276#define MSTPCR5_HSCIF0 BIT(14)
277#define MSTPCR6_INTCEX BIT(11)
278#define MSTPCR7_SCIF0 BIT(2)
279
280static const struct mstp_stop_table r8a779h0_mstp_table[] = {
281 { 0x0FC102A1, 0x0, 0x0, 0x0 },
282 { 0x00D50020, 0x0, 0x0, 0x0 },
283 { 0x00003800, 0x0, 0x0, 0x0 },
284 { 0xF0000000, 0x0, 0x0, 0x0 },
285 { 0x0000CA01, 0x0, 0x0, 0x0 },
286 { 0xE63FE100, MSTPCR5_HSCIF0 | MSTPCR5_INTCAP, 0x0, 0x0 },
287 { 0xF1FF3900, MSTPCR6_INTCEX, 0x0, 0x0 },
288 { 0xDFF7E6FC, MSTPCR7_SCIF0, 0x0, 0x0 },
289 { 0x40003FFF, 0x0, 0x0, 0x0 },
290 { 0x001BBCF8, 0x0, 0x0, 0x0 },
291 { 0x10000000, 0x0, 0x0, 0x0 },
292 { 0x00000001, 0x0, 0x0, 0x0 },
293 { 0xDE000000, 0x0, 0x0, 0x0 },
294 { 0x00000017, 0x0, 0x0, 0x0 },
295 { 0x00000000, 0x0, 0x0, 0x0 },
296 { 0x00000000, 0x0, 0x0, 0x0 },
297 { 0x00000000, 0x0, 0x0, 0x0 },
298 { 0x00000000, 0x0, 0x0, 0x0 },
299 { 0x00000000, 0x0, 0x0, 0x0 },
300 { 0x00000000, 0x0, 0x0, 0x0 },
301 { 0x00000000, 0x0, 0x0, 0x0 },
302 { 0x00000000, 0x0, 0x0, 0x0 },
303 { 0x00000000, 0x0, 0x0, 0x0 },
304 { 0x00000000, 0x0, 0x0, 0x0 },
305 { 0x00000000, 0x0, 0x0, 0x0 },
306 { 0x00000000, 0x0, 0x0, 0x0 },
307 { 0x00000000, 0x0, 0x0, 0x0 },
308 { 0x308003C0, 0x0, 0x0, 0x0 },
309 { 0x402200E6, 0x0, 0x0, 0x0 },
310 { 0x0C000000, 0x0, 0x0, 0x0 },
311};
312
313static const void *r8a779h0_get_pll_config(const u32 cpg_mode)
314{
315 return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
316}
317
318static const struct cpg_mssr_info r8a779h0_cpg_mssr_info = {
319 .core_clk = r8a779h0_core_clks,
320 .core_clk_size = ARRAY_SIZE(r8a779h0_core_clks),
321 .mod_clk = r8a779h0_mod_clks,
322 .mod_clk_size = ARRAY_SIZE(r8a779h0_mod_clks),
323 .mstp_table = r8a779h0_mstp_table,
324 .mstp_table_size = ARRAY_SIZE(r8a779h0_mstp_table),
325 .reset_node = "renesas,r8a779h0-rst",
326 .reset_modemr_offset = CPG_RST_MODEMR0,
327 .extalr_node = "extalr",
328 .mod_clk_base = MOD_CLK_BASE,
329 .clk_extal_id = CLK_EXTAL,
330 .clk_extalr_id = CLK_EXTALR,
331 .get_pll_config = r8a779h0_get_pll_config,
332 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
333};
334
335static const struct udevice_id r8a779h0_cpg_ids[] = {
336 {
337 .compatible = "renesas,r8a779h0-cpg-mssr",
338 .data = (ulong)&r8a779h0_cpg_mssr_info
339 },
340 { }
341};
342
343U_BOOT_DRIVER(clk_r8a779h0) = {
344 .name = "cpg_r8a779h0",
345 .id = UCLASS_NOP,
346 .of_match = r8a779h0_cpg_ids,
347 .bind = gen3_cpg_bind,
348};