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Andreas Färber9e3ad682017-05-15 17:51:18 +08001/*
2 * Copyright (c) 2016 Andreas Färber
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __CONFIG_RK3368_COMMON_H
8#define __CONFIG_RK3368_COMMON_H
9
Klaus Gogera850b2b2017-10-06 19:24:09 +020010#include "rockchip-common.h"
11
Andreas Färber9e3ad682017-05-15 17:51:18 +080012#define CONFIG_SYS_CACHELINE_SIZE 64
13
14#include <asm/arch/hardware.h>
15#include <linux/sizes.h>
16
Kever Yang5db9e672017-06-23 16:11:05 +080017#define CONFIG_SYS_SDRAM_BASE 0
18#define SDRAM_MAX_SIZE 0xff000000
Andreas Färber9e3ad682017-05-15 17:51:18 +080019#define CONFIG_NR_DRAM_BANKS 1
Andreas Färber9e3ad682017-05-15 17:51:18 +080020#define CONFIG_BAUDRATE 115200
21#define CONFIG_SYS_MALLOC_LEN (32 << 20)
22#define CONFIG_SYS_CBSIZE 1024
23#define CONFIG_SKIP_LOWLEVEL_INIT
24
Philipp Tomsich9b687c72017-06-22 23:31:55 +020025#define COUNTER_FREQUENCY 24000000
26
Andreas Färber9e3ad682017-05-15 17:51:18 +080027#define CONFIG_SYS_NS16550_MEM32
28
Andreas Färber9e3ad682017-05-15 17:51:18 +080029#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
30#define CONFIG_SYS_LOAD_ADDR 0x00280000
31
Philipp Tomsich0c1c09f2017-07-14 17:52:09 +020032#define CONFIG_SPL_TEXT_BASE 0x00000000
33#define CONFIG_SPL_MAX_SIZE 0x40000
34#define CONFIG_SPL_BSS_START_ADDR 0x400000
35#define CONFIG_SPL_BSS_MAX_SIZE 0x20000
36
Andreas Färber9e3ad682017-05-15 17:51:18 +080037#define CONFIG_BOUNCE_BUFFER
38
39#ifndef CONFIG_SPL_BUILD
40#define ENV_MEM_LAYOUT_SETTINGS \
41 "scriptaddr=0x00500000\0" \
42 "pxefile_addr_r=0x00600000\0" \
43 "fdt_addr_r=0x5600000\0" \
44 "kernel_addr_r=0x280000\0" \
45 "ramdisk_addr_r=0x5bf0000\0"
46
Andreas Färber9e3ad682017-05-15 17:51:18 +080047#include <config_distro_bootcmd.h>
48
49#define CONFIG_EXTRA_ENV_SETTINGS \
Andy Yanc35846d2017-09-04 20:32:23 +080050 ENV_MEM_LAYOUT_SETTINGS \
Andreas Färber9e3ad682017-05-15 17:51:18 +080051 BOOTENV
52
53#endif
54
55#endif