blob: 0e4c431cabf7cb88b5c22d152521b35db5c2418f [file] [log] [blame]
Rick Chenb46a18b2017-12-26 13:55:54 +08001/*
2 * Copyright (C) 2017 Andes Technology Corporation
3 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11/*
12 * CPU and Board Configuration Options
13 */
Rick Chenb46a18b2017-12-26 13:55:54 +080014#define CONFIG_BOOTP_SEND_HOSTNAME
15#define CONFIG_BOOTP_SERVERIP
16
Rick Chenb46a18b2017-12-26 13:55:54 +080017/*
18 * Miscellaneous configurable options
19 */
Rick Chenb46a18b2017-12-26 13:55:54 +080020#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
21
22/*
23 * Print Buffer Size
24 */
25#define CONFIG_SYS_PBSIZE \
26 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
27
28/*
29 * max number of command args
30 */
31#define CONFIG_SYS_MAXARGS 16
32
33/*
34 * Boot Argument Buffer Size
35 */
36#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
37
38/*
39 * Size of malloc() pool
40 * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough
41 */
42#define CONFIG_SYS_MALLOC_LEN (512 << 10)
43
Rick Chen40a6fe72018-03-29 10:08:33 +080044/* DT blob (fdt) address */
45#define CONFIG_SYS_FDT_BASE 0x000f0000
46
Rick Chenb46a18b2017-12-26 13:55:54 +080047/*
48 * Physical Memory Map
49 */
50#define CONFIG_NR_DRAM_BANKS 2
51#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
52#define PHYS_SDRAM_1 \
53 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
54#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
55#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
56#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
57
58/*
59 * Serial console configuration
60 */
Rick Chenb46a18b2017-12-26 13:55:54 +080061#define CONFIG_SYS_NS16550_SERIAL
62#ifndef CONFIG_DM_SERIAL
63#define CONFIG_SYS_NS16550_REG_SIZE -4
64#endif
65#define CONFIG_SYS_NS16550_CLK 19660800
66
Rick Chenb46a18b2017-12-26 13:55:54 +080067/* Init Stack Pointer */
68#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \
69 GENERATED_GBL_DATA_SIZE)
70
71/*
72 * Load address and memory test area should agree with
73 * arch/riscv/config.mk. Be careful not to overwrite U-Boot itself.
74 */
75#define CONFIG_SYS_LOAD_ADDR 0x100000 /* SDRAM */
76
77/*
78 * memtest works on 512 MB in DRAM
79 */
80#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
81#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)
82
83/* environments */
84#define CONFIG_ENV_SPI_BUS 0
85#define CONFIG_ENV_SPI_CS 0
86#define CONFIG_ENV_SPI_MAX_HZ 50000000
87#define CONFIG_ENV_SPI_MODE 0
88#define CONFIG_ENV_SECT_SIZE 0x1000
89#define CONFIG_ENV_OVERWRITE
90
91/* SPI FLASH */
92#define CONFIG_SF_DEFAULT_BUS 0
93#define CONFIG_SF_DEFAULT_CS 0
94#define CONFIG_SF_DEFAULT_SPEED 1000000
95#define CONFIG_SF_DEFAULT_MODE 0
96
97/*
98 * For booting Linux, the board info and command line data
99 * have to be in the first 16 MB of memory, since this is
100 * the maximum mapped by the Linux kernel during initialization.
101 */
102
103/* Initial Memory map for Linux*/
104#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
105/* Increase max gunzip size */
106#define CONFIG_SYS_BOOTM_LEN (64 << 20)
107
108#endif /* __CONFIG_H */