Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Freescale i.MX28 GPIO control code |
| 4 | * |
| 5 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> |
| 6 | * on behalf of DENX Software Engineering GmbH |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <common.h> |
Masahiro Yamada | 56a931c | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 10 | #include <linux/errno.h> |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 11 | #include <asm/io.h> |
| 12 | #include <asm/arch/iomux.h> |
| 13 | #include <asm/arch/imx-regs.h> |
| 14 | |
| 15 | #if defined(CONFIG_MX23) |
| 16 | #define PINCTRL_BANKS 3 |
| 17 | #define PINCTRL_DOUT(n) (0x0500 + ((n) * 0x10)) |
| 18 | #define PINCTRL_DIN(n) (0x0600 + ((n) * 0x10)) |
| 19 | #define PINCTRL_DOE(n) (0x0700 + ((n) * 0x10)) |
| 20 | #define PINCTRL_PIN2IRQ(n) (0x0800 + ((n) * 0x10)) |
| 21 | #define PINCTRL_IRQEN(n) (0x0900 + ((n) * 0x10)) |
| 22 | #define PINCTRL_IRQSTAT(n) (0x0c00 + ((n) * 0x10)) |
| 23 | #elif defined(CONFIG_MX28) |
| 24 | #define PINCTRL_BANKS 5 |
| 25 | #define PINCTRL_DOUT(n) (0x0700 + ((n) * 0x10)) |
| 26 | #define PINCTRL_DIN(n) (0x0900 + ((n) * 0x10)) |
| 27 | #define PINCTRL_DOE(n) (0x0b00 + ((n) * 0x10)) |
| 28 | #define PINCTRL_PIN2IRQ(n) (0x1000 + ((n) * 0x10)) |
| 29 | #define PINCTRL_IRQEN(n) (0x1100 + ((n) * 0x10)) |
| 30 | #define PINCTRL_IRQSTAT(n) (0x1400 + ((n) * 0x10)) |
| 31 | #else |
| 32 | #error "Please select CONFIG_MX23 or CONFIG_MX28" |
| 33 | #endif |
| 34 | |
| 35 | #define GPIO_INT_FALL_EDGE 0x0 |
| 36 | #define GPIO_INT_LOW_LEV 0x1 |
| 37 | #define GPIO_INT_RISE_EDGE 0x2 |
| 38 | #define GPIO_INT_HIGH_LEV 0x3 |
| 39 | #define GPIO_INT_LEV_MASK (1 << 0) |
| 40 | #define GPIO_INT_POL_MASK (1 << 1) |
| 41 | |
| 42 | void mxs_gpio_init(void) |
| 43 | { |
| 44 | int i; |
| 45 | |
| 46 | for (i = 0; i < PINCTRL_BANKS; i++) { |
| 47 | writel(0, MXS_PINCTRL_BASE + PINCTRL_PIN2IRQ(i)); |
| 48 | writel(0, MXS_PINCTRL_BASE + PINCTRL_IRQEN(i)); |
| 49 | /* Use SCT address here to clear the IRQSTAT bits */ |
| 50 | writel(0xffffffff, MXS_PINCTRL_BASE + PINCTRL_IRQSTAT(i) + 8); |
| 51 | } |
| 52 | } |
| 53 | |
Lukasz Majewski | e5c207c | 2019-06-19 17:31:05 +0200 | [diff] [blame] | 54 | #if !CONFIG_IS_ENABLED(DM_GPIO) |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 55 | int gpio_get_value(unsigned gpio) |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 56 | { |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 57 | uint32_t bank = PAD_BANK(gpio); |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 58 | uint32_t offset = PINCTRL_DIN(bank); |
Otavio Salvador | 5309b00 | 2012-08-05 09:05:30 +0000 | [diff] [blame] | 59 | struct mxs_register_32 *reg = |
| 60 | (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset); |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 61 | |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 62 | return (readl(®->reg) >> PAD_PIN(gpio)) & 1; |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 63 | } |
| 64 | |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 65 | void gpio_set_value(unsigned gpio, int value) |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 66 | { |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 67 | uint32_t bank = PAD_BANK(gpio); |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 68 | uint32_t offset = PINCTRL_DOUT(bank); |
Otavio Salvador | 5309b00 | 2012-08-05 09:05:30 +0000 | [diff] [blame] | 69 | struct mxs_register_32 *reg = |
| 70 | (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset); |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 71 | |
| 72 | if (value) |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 73 | writel(1 << PAD_PIN(gpio), ®->reg_set); |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 74 | else |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 75 | writel(1 << PAD_PIN(gpio), ®->reg_clr); |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 76 | } |
| 77 | |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 78 | int gpio_direction_input(unsigned gpio) |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 79 | { |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 80 | uint32_t bank = PAD_BANK(gpio); |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 81 | uint32_t offset = PINCTRL_DOE(bank); |
Otavio Salvador | 5309b00 | 2012-08-05 09:05:30 +0000 | [diff] [blame] | 82 | struct mxs_register_32 *reg = |
| 83 | (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset); |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 84 | |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 85 | writel(1 << PAD_PIN(gpio), ®->reg_clr); |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 86 | |
| 87 | return 0; |
| 88 | } |
| 89 | |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 90 | int gpio_direction_output(unsigned gpio, int value) |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 91 | { |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 92 | uint32_t bank = PAD_BANK(gpio); |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 93 | uint32_t offset = PINCTRL_DOE(bank); |
Otavio Salvador | 5309b00 | 2012-08-05 09:05:30 +0000 | [diff] [blame] | 94 | struct mxs_register_32 *reg = |
| 95 | (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset); |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 96 | |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 97 | gpio_set_value(gpio, value); |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 98 | |
Michael Heimpold | 041487c | 2013-11-03 22:59:26 +0100 | [diff] [blame] | 99 | writel(1 << PAD_PIN(gpio), ®->reg_set); |
| 100 | |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 101 | return 0; |
| 102 | } |
| 103 | |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 104 | int gpio_request(unsigned gpio, const char *label) |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 105 | { |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 106 | if (PAD_BANK(gpio) >= PINCTRL_BANKS) |
| 107 | return -1; |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 108 | |
| 109 | return 0; |
| 110 | } |
| 111 | |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 112 | int gpio_free(unsigned gpio) |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 113 | { |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 114 | return 0; |
Marek Vasut | 53fdab2 | 2011-11-08 23:18:13 +0000 | [diff] [blame] | 115 | } |
Måns Rullgård | a7ec686 | 2015-12-15 22:27:57 +0000 | [diff] [blame] | 116 | |
| 117 | int name_to_gpio(const char *name) |
| 118 | { |
| 119 | unsigned bank, pin; |
| 120 | char *end; |
| 121 | |
| 122 | bank = simple_strtoul(name, &end, 10); |
| 123 | |
| 124 | if (!*end || *end != ':') |
| 125 | return bank; |
| 126 | |
| 127 | pin = simple_strtoul(end + 1, NULL, 10); |
| 128 | |
| 129 | return (bank << MXS_PAD_BANK_SHIFT) | (pin << MXS_PAD_PIN_SHIFT); |
| 130 | } |
Simon Glass | fa4689a | 2019-12-06 21:41:35 -0700 | [diff] [blame] | 131 | #else /* DM_GPIO */ |
Lukasz Majewski | e5c207c | 2019-06-19 17:31:05 +0200 | [diff] [blame] | 132 | #include <dm.h> |
| 133 | #include <asm/gpio.h> |
Lukasz Majewski | 70a3030 | 2019-09-05 09:55:01 +0200 | [diff] [blame] | 134 | #include <dt-structs.h> |
Lukasz Majewski | e5c207c | 2019-06-19 17:31:05 +0200 | [diff] [blame] | 135 | #include <asm/arch/gpio.h> |
| 136 | #define MXS_MAX_GPIO_PER_BANK 32 |
| 137 | |
Lukasz Majewski | 70a3030 | 2019-09-05 09:55:01 +0200 | [diff] [blame] | 138 | #ifdef CONFIG_MX28 |
| 139 | #define dtd_fsl_imx_gpio dtd_fsl_imx28_gpio |
| 140 | #else /* CONFIG_MX23 */ |
| 141 | #define dtd_fsl_imx_gpio dtd_fsl_imx23_gpio |
| 142 | #endif |
| 143 | |
Lukasz Majewski | e5c207c | 2019-06-19 17:31:05 +0200 | [diff] [blame] | 144 | DECLARE_GLOBAL_DATA_PTR; |
| 145 | /* |
| 146 | * According to i.MX28 Reference Manual: |
| 147 | * 'i.MX28 Applications Processor Reference Manual, Rev. 1, 2010' |
| 148 | * The i.MX28 has following number of GPIOs available: |
| 149 | * Bank 0: 0-28 -> 29 PINS |
| 150 | * Bank 1: 0-31 -> 32 PINS |
| 151 | * Bank 2: 0-27 -> 28 PINS |
| 152 | * Bank 3: 0-30 -> 31 PINS |
| 153 | * Bank 4: 0-20 -> 21 PINS |
| 154 | */ |
| 155 | |
Lukasz Majewski | 70a3030 | 2019-09-05 09:55:01 +0200 | [diff] [blame] | 156 | struct mxs_gpio_platdata { |
| 157 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 158 | struct dtd_fsl_imx_gpio dtplat; |
| 159 | #endif |
| 160 | unsigned int bank; |
| 161 | int gpio_ranges; |
| 162 | }; |
| 163 | |
Lukasz Majewski | e5c207c | 2019-06-19 17:31:05 +0200 | [diff] [blame] | 164 | struct mxs_gpio_priv { |
| 165 | unsigned int bank; |
| 166 | }; |
| 167 | |
| 168 | static int mxs_gpio_get_value(struct udevice *dev, unsigned offset) |
| 169 | { |
| 170 | struct mxs_gpio_priv *priv = dev_get_priv(dev); |
| 171 | struct mxs_register_32 *reg = |
| 172 | (struct mxs_register_32 *)(MXS_PINCTRL_BASE + |
| 173 | PINCTRL_DIN(priv->bank)); |
| 174 | |
| 175 | return (readl(®->reg) >> offset) & 1; |
| 176 | } |
| 177 | |
| 178 | static int mxs_gpio_set_value(struct udevice *dev, unsigned offset, |
| 179 | int value) |
| 180 | { |
| 181 | struct mxs_gpio_priv *priv = dev_get_priv(dev); |
| 182 | struct mxs_register_32 *reg = |
| 183 | (struct mxs_register_32 *)(MXS_PINCTRL_BASE + |
| 184 | PINCTRL_DOUT(priv->bank)); |
| 185 | if (value) |
| 186 | writel(BIT(offset), ®->reg_set); |
| 187 | else |
| 188 | writel(BIT(offset), ®->reg_clr); |
| 189 | |
| 190 | return 0; |
| 191 | } |
| 192 | |
| 193 | static int mxs_gpio_direction_input(struct udevice *dev, unsigned offset) |
| 194 | { |
| 195 | struct mxs_gpio_priv *priv = dev_get_priv(dev); |
| 196 | struct mxs_register_32 *reg = |
| 197 | (struct mxs_register_32 *)(MXS_PINCTRL_BASE + |
| 198 | PINCTRL_DOE(priv->bank)); |
| 199 | |
| 200 | writel(BIT(offset), ®->reg_clr); |
| 201 | |
| 202 | return 0; |
| 203 | } |
| 204 | |
| 205 | static int mxs_gpio_direction_output(struct udevice *dev, unsigned offset, |
| 206 | int value) |
| 207 | { |
| 208 | struct mxs_gpio_priv *priv = dev_get_priv(dev); |
| 209 | struct mxs_register_32 *reg = |
| 210 | (struct mxs_register_32 *)(MXS_PINCTRL_BASE + |
| 211 | PINCTRL_DOE(priv->bank)); |
| 212 | |
| 213 | mxs_gpio_set_value(dev, offset, value); |
| 214 | |
| 215 | writel(BIT(offset), ®->reg_set); |
| 216 | |
| 217 | return 0; |
| 218 | } |
| 219 | |
| 220 | static int mxs_gpio_get_function(struct udevice *dev, unsigned offset) |
| 221 | { |
| 222 | struct mxs_gpio_priv *priv = dev_get_priv(dev); |
| 223 | struct mxs_register_32 *reg = |
| 224 | (struct mxs_register_32 *)(MXS_PINCTRL_BASE + |
| 225 | PINCTRL_DOE(priv->bank)); |
| 226 | bool is_output = !!(readl(®->reg) >> offset); |
| 227 | |
| 228 | return is_output ? GPIOF_OUTPUT : GPIOF_INPUT; |
| 229 | } |
| 230 | |
| 231 | static const struct dm_gpio_ops gpio_mxs_ops = { |
| 232 | .direction_input = mxs_gpio_direction_input, |
| 233 | .direction_output = mxs_gpio_direction_output, |
| 234 | .get_value = mxs_gpio_get_value, |
| 235 | .set_value = mxs_gpio_set_value, |
| 236 | .get_function = mxs_gpio_get_function, |
| 237 | }; |
| 238 | |
| 239 | static int mxs_gpio_probe(struct udevice *dev) |
| 240 | { |
Lukasz Majewski | 70a3030 | 2019-09-05 09:55:01 +0200 | [diff] [blame] | 241 | struct mxs_gpio_platdata *plat = dev_get_platdata(dev); |
Lukasz Majewski | e5c207c | 2019-06-19 17:31:05 +0200 | [diff] [blame] | 242 | struct mxs_gpio_priv *priv = dev_get_priv(dev); |
| 243 | struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); |
Lukasz Majewski | e5c207c | 2019-06-19 17:31:05 +0200 | [diff] [blame] | 244 | char name[16], *str; |
Lukasz Majewski | e5c207c | 2019-06-19 17:31:05 +0200 | [diff] [blame] | 245 | |
Lukasz Majewski | 70a3030 | 2019-09-05 09:55:01 +0200 | [diff] [blame] | 246 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 247 | struct dtd_fsl_imx_gpio *dtplat = &plat->dtplat; |
| 248 | priv->bank = (unsigned int)dtplat->reg[0]; |
| 249 | uc_priv->gpio_count = dtplat->gpio_ranges[3]; |
| 250 | #else |
| 251 | priv->bank = (unsigned int)plat->bank; |
| 252 | uc_priv->gpio_count = plat->gpio_ranges; |
| 253 | #endif |
Lukasz Majewski | e5c207c | 2019-06-19 17:31:05 +0200 | [diff] [blame] | 254 | snprintf(name, sizeof(name), "GPIO%d_", priv->bank); |
| 255 | str = strdup(name); |
| 256 | if (!str) |
| 257 | return -ENOMEM; |
| 258 | |
| 259 | uc_priv->bank_name = str; |
| 260 | |
Lukasz Majewski | 70a3030 | 2019-09-05 09:55:01 +0200 | [diff] [blame] | 261 | debug("%s: %s: %d pins base: 0x%x\n", __func__, uc_priv->bank_name, |
| 262 | uc_priv->gpio_count, priv->bank); |
| 263 | |
| 264 | return 0; |
| 265 | } |
| 266 | |
| 267 | #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) |
| 268 | static int mxs_ofdata_to_platdata(struct udevice *dev) |
| 269 | { |
| 270 | struct mxs_gpio_platdata *plat = dev->platdata; |
| 271 | struct fdtdec_phandle_args args; |
| 272 | int node = dev_of_offset(dev); |
| 273 | int ret; |
| 274 | |
| 275 | plat->bank = devfdt_get_addr(dev); |
| 276 | if (plat->bank == FDT_ADDR_T_NONE) { |
| 277 | printf("%s: No 'reg' property defined!\n", __func__); |
| 278 | return -EINVAL; |
| 279 | } |
| 280 | |
Lukasz Majewski | e5c207c | 2019-06-19 17:31:05 +0200 | [diff] [blame] | 281 | ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges", |
| 282 | NULL, 3, 0, &args); |
| 283 | if (ret) |
| 284 | printf("%s: 'gpio-ranges' not defined - using default!\n", |
| 285 | __func__); |
| 286 | |
Lukasz Majewski | 70a3030 | 2019-09-05 09:55:01 +0200 | [diff] [blame] | 287 | plat->gpio_ranges = ret == 0 ? args.args[2] : MXS_MAX_GPIO_PER_BANK; |
Lukasz Majewski | e5c207c | 2019-06-19 17:31:05 +0200 | [diff] [blame] | 288 | |
| 289 | return 0; |
| 290 | } |
| 291 | |
| 292 | static const struct udevice_id mxs_gpio_ids[] = { |
| 293 | { .compatible = "fsl,imx23-gpio" }, |
| 294 | { .compatible = "fsl,imx28-gpio" }, |
| 295 | { } |
| 296 | }; |
Lukasz Majewski | 70a3030 | 2019-09-05 09:55:01 +0200 | [diff] [blame] | 297 | #endif |
Lukasz Majewski | e5c207c | 2019-06-19 17:31:05 +0200 | [diff] [blame] | 298 | |
| 299 | U_BOOT_DRIVER(gpio_mxs) = { |
Lukasz Majewski | 70a3030 | 2019-09-05 09:55:01 +0200 | [diff] [blame] | 300 | #ifdef CONFIG_MX28 |
| 301 | .name = "fsl_imx28_gpio", |
| 302 | #else /* CONFIG_MX23 */ |
| 303 | .name = "fsl_imx23_gpio", |
| 304 | #endif |
Lukasz Majewski | e5c207c | 2019-06-19 17:31:05 +0200 | [diff] [blame] | 305 | .id = UCLASS_GPIO, |
| 306 | .ops = &gpio_mxs_ops, |
| 307 | .probe = mxs_gpio_probe, |
| 308 | .priv_auto_alloc_size = sizeof(struct mxs_gpio_priv), |
Lukasz Majewski | 70a3030 | 2019-09-05 09:55:01 +0200 | [diff] [blame] | 309 | .platdata_auto_alloc_size = sizeof(struct mxs_gpio_platdata), |
| 310 | #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) |
Lukasz Majewski | e5c207c | 2019-06-19 17:31:05 +0200 | [diff] [blame] | 311 | .of_match = mxs_gpio_ids, |
Lukasz Majewski | 70a3030 | 2019-09-05 09:55:01 +0200 | [diff] [blame] | 312 | .ofdata_to_platdata = mxs_ofdata_to_platdata, |
| 313 | #endif |
Lukasz Majewski | e5c207c | 2019-06-19 17:31:05 +0200 | [diff] [blame] | 314 | }; |
Simon Glass | fa4689a | 2019-12-06 21:41:35 -0700 | [diff] [blame] | 315 | #endif /* DM_GPIO */ |