Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2015 Freescale Semiconductor |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 4 | */ |
| 5 | #include <common.h> |
Simon Glass | 0af6e2d | 2019-08-01 09:46:52 -0600 | [diff] [blame] | 6 | #include <env.h> |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 7 | #include <malloc.h> |
| 8 | #include <errno.h> |
| 9 | #include <netdev.h> |
| 10 | #include <fsl_ifc.h> |
| 11 | #include <fsl_ddr.h> |
| 12 | #include <asm/io.h> |
| 13 | #include <fdt_support.h> |
Masahiro Yamada | 75f82d0 | 2018-03-05 01:20:11 +0900 | [diff] [blame] | 14 | #include <linux/libfdt.h> |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 15 | #include <fsl-mc/fsl_mc.h> |
Simon Glass | 9d1f619 | 2019-08-02 09:44:25 -0600 | [diff] [blame] | 16 | #include <env_internal.h> |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 17 | #include <i2c.h> |
Priyanka Jain | 2657e43 | 2015-06-29 15:39:40 +0530 | [diff] [blame] | 18 | #include <rtc.h> |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 19 | #include <asm/arch/soc.h> |
Haikun Wang | a6cd9da | 2015-06-26 19:58:12 +0800 | [diff] [blame] | 20 | #include <hwconfig.h> |
Saksham Jain | c0c38d2 | 2016-03-23 16:24:35 +0530 | [diff] [blame] | 21 | #include <fsl_sec.h> |
Santan Kumar | c61c699 | 2017-03-07 11:21:03 +0530 | [diff] [blame] | 22 | #include <asm/arch/ppa.h> |
Laurentiu Tudor | 4adff39 | 2019-10-18 09:01:54 +0000 | [diff] [blame] | 23 | #include <asm/arch-fsl-layerscape/fsl_icid.h> |
Santan Kumar | c61c699 | 2017-03-07 11:21:03 +0530 | [diff] [blame] | 24 | |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 25 | |
| 26 | #include "../common/qixis.h" |
Prabhakar Kushwaha | 122bcfd | 2015-11-09 16:42:07 +0530 | [diff] [blame] | 27 | #include "ls2080aqds_qixis.h" |
Priyanka Jain | 53e7ec0 | 2017-01-19 11:12:28 +0530 | [diff] [blame] | 28 | #include "../common/vid.h" |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 29 | |
Haikun Wang | a6cd9da | 2015-06-26 19:58:12 +0800 | [diff] [blame] | 30 | #define PIN_MUX_SEL_SDHC 0x00 |
| 31 | #define PIN_MUX_SEL_DSPI 0x0a |
Yuan Yao | 2ec8584 | 2016-06-08 18:24:52 +0800 | [diff] [blame] | 32 | #define SCFG_QSPICLKCTRL_DIV_20 (5 << 27) |
Haikun Wang | a6cd9da | 2015-06-26 19:58:12 +0800 | [diff] [blame] | 33 | |
| 34 | #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value) |
| 35 | |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 36 | DECLARE_GLOBAL_DATA_PTR; |
| 37 | |
Haikun Wang | a6cd9da | 2015-06-26 19:58:12 +0800 | [diff] [blame] | 38 | enum { |
| 39 | MUX_TYPE_SDHC, |
| 40 | MUX_TYPE_DSPI, |
| 41 | }; |
| 42 | |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 43 | unsigned long long get_qixis_addr(void) |
| 44 | { |
| 45 | unsigned long long addr; |
| 46 | |
| 47 | if (gd->flags & GD_FLG_RELOC) |
| 48 | addr = QIXIS_BASE_PHYS; |
| 49 | else |
| 50 | addr = QIXIS_BASE_PHYS_EARLY; |
| 51 | |
| 52 | /* |
| 53 | * IFC address under 256MB is mapped to 0x30000000, any address above |
| 54 | * is mapped to 0x5_10000000 up to 4GB. |
| 55 | */ |
| 56 | addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; |
| 57 | |
| 58 | return addr; |
| 59 | } |
| 60 | |
| 61 | int checkboard(void) |
| 62 | { |
| 63 | char buf[64]; |
| 64 | u8 sw; |
| 65 | static const char *const freq[] = {"100", "125", "156.25", |
| 66 | "100 separate SSCG"}; |
| 67 | int clock; |
| 68 | |
Prabhakar Kushwaha | 67f2e9c | 2015-05-28 14:54:07 +0530 | [diff] [blame] | 69 | cpu_name(buf); |
| 70 | printf("Board: %s-QDS, ", buf); |
| 71 | |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 72 | sw = QIXIS_READ(arch); |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 73 | printf("Board Arch: V%d, ", sw >> 4); |
| 74 | printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); |
| 75 | |
Prabhakar Kushwaha | 67f2e9c | 2015-05-28 14:54:07 +0530 | [diff] [blame] | 76 | memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); |
| 77 | |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 78 | sw = QIXIS_READ(brdcfg[0]); |
| 79 | sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; |
| 80 | |
| 81 | if (sw < 0x8) |
| 82 | printf("vBank: %d\n", sw); |
| 83 | else if (sw == 0x8) |
| 84 | puts("PromJet\n"); |
| 85 | else if (sw == 0x9) |
| 86 | puts("NAND\n"); |
Yuan Yao | 331c87c | 2016-06-08 18:25:00 +0800 | [diff] [blame] | 87 | else if (sw == 0xf) |
| 88 | puts("QSPI\n"); |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 89 | else if (sw == 0x15) |
| 90 | printf("IFCCard\n"); |
| 91 | else |
| 92 | printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); |
| 93 | |
| 94 | printf("FPGA: v%d (%s), build %d", |
| 95 | (int)QIXIS_READ(scver), qixis_read_tag(buf), |
| 96 | (int)qixis_read_minor()); |
| 97 | /* the timestamp string contains "\n" at the end */ |
| 98 | printf(" on %s", qixis_read_time(buf)); |
| 99 | |
| 100 | /* |
| 101 | * Display the actual SERDES reference clocks as configured by the |
| 102 | * dip switches on the board. Note that the SWx registers could |
| 103 | * technically be set to force the reference clocks to match the |
| 104 | * values that the SERDES expects (or vice versa). For now, however, |
| 105 | * we just display both values and hope the user notices when they |
| 106 | * don't match. |
| 107 | */ |
| 108 | puts("SERDES1 Reference : "); |
| 109 | sw = QIXIS_READ(brdcfg[2]); |
| 110 | clock = (sw >> 6) & 3; |
| 111 | printf("Clock1 = %sMHz ", freq[clock]); |
| 112 | clock = (sw >> 4) & 3; |
| 113 | printf("Clock2 = %sMHz", freq[clock]); |
| 114 | |
| 115 | puts("\nSERDES2 Reference : "); |
| 116 | clock = (sw >> 2) & 3; |
| 117 | printf("Clock1 = %sMHz ", freq[clock]); |
| 118 | clock = (sw >> 0) & 3; |
| 119 | printf("Clock2 = %sMHz\n", freq[clock]); |
| 120 | |
| 121 | return 0; |
| 122 | } |
| 123 | |
| 124 | unsigned long get_board_sys_clk(void) |
| 125 | { |
| 126 | u8 sysclk_conf = QIXIS_READ(brdcfg[1]); |
| 127 | |
| 128 | switch (sysclk_conf & 0x0F) { |
| 129 | case QIXIS_SYSCLK_83: |
| 130 | return 83333333; |
| 131 | case QIXIS_SYSCLK_100: |
| 132 | return 100000000; |
| 133 | case QIXIS_SYSCLK_125: |
| 134 | return 125000000; |
| 135 | case QIXIS_SYSCLK_133: |
| 136 | return 133333333; |
| 137 | case QIXIS_SYSCLK_150: |
| 138 | return 150000000; |
| 139 | case QIXIS_SYSCLK_160: |
| 140 | return 160000000; |
| 141 | case QIXIS_SYSCLK_166: |
| 142 | return 166666666; |
| 143 | } |
| 144 | return 66666666; |
| 145 | } |
| 146 | |
| 147 | unsigned long get_board_ddr_clk(void) |
| 148 | { |
| 149 | u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); |
| 150 | |
| 151 | switch ((ddrclk_conf & 0x30) >> 4) { |
| 152 | case QIXIS_DDRCLK_100: |
| 153 | return 100000000; |
| 154 | case QIXIS_DDRCLK_125: |
| 155 | return 125000000; |
| 156 | case QIXIS_DDRCLK_133: |
| 157 | return 133333333; |
| 158 | } |
| 159 | return 66666666; |
| 160 | } |
| 161 | |
| 162 | int select_i2c_ch_pca9547(u8 ch) |
| 163 | { |
| 164 | int ret; |
Chuanhua Han | 1ab68c7 | 2019-07-26 19:24:01 +0800 | [diff] [blame] | 165 | #ifdef CONFIG_DM_I2C |
| 166 | struct udevice *dev; |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 167 | |
Chuanhua Han | 1ab68c7 | 2019-07-26 19:24:01 +0800 | [diff] [blame] | 168 | ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); |
| 169 | if (!ret) |
| 170 | ret = dm_i2c_write(dev, 0, &ch, 1); |
| 171 | |
| 172 | #else |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 173 | ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); |
Chuanhua Han | 1ab68c7 | 2019-07-26 19:24:01 +0800 | [diff] [blame] | 174 | #endif |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 175 | if (ret) { |
| 176 | puts("PCA: failed to select proper channel\n"); |
| 177 | return ret; |
| 178 | } |
| 179 | |
| 180 | return 0; |
| 181 | } |
| 182 | |
Haikun Wang | a6cd9da | 2015-06-26 19:58:12 +0800 | [diff] [blame] | 183 | int config_board_mux(int ctrl_type) |
| 184 | { |
| 185 | u8 reg5; |
| 186 | |
| 187 | reg5 = QIXIS_READ(brdcfg[5]); |
| 188 | |
| 189 | switch (ctrl_type) { |
| 190 | case MUX_TYPE_SDHC: |
| 191 | reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); |
| 192 | break; |
| 193 | case MUX_TYPE_DSPI: |
| 194 | reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); |
| 195 | break; |
| 196 | default: |
| 197 | printf("Wrong mux interface type\n"); |
| 198 | return -1; |
| 199 | } |
| 200 | |
| 201 | QIXIS_WRITE(brdcfg[5], reg5); |
| 202 | |
| 203 | return 0; |
| 204 | } |
| 205 | |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 206 | int board_init(void) |
| 207 | { |
Haikun Wang | a6cd9da | 2015-06-26 19:58:12 +0800 | [diff] [blame] | 208 | char *env_hwconfig; |
| 209 | u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; |
| 210 | u32 val; |
| 211 | |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 212 | init_final_memctl_regs(); |
| 213 | |
Haikun Wang | a6cd9da | 2015-06-26 19:58:12 +0800 | [diff] [blame] | 214 | val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); |
| 215 | |
Simon Glass | 64b723f | 2017-08-03 12:22:12 -0600 | [diff] [blame] | 216 | env_hwconfig = env_get("hwconfig"); |
Haikun Wang | a6cd9da | 2015-06-26 19:58:12 +0800 | [diff] [blame] | 217 | |
| 218 | if (hwconfig_f("dspi", env_hwconfig) && |
| 219 | DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) |
| 220 | config_board_mux(MUX_TYPE_DSPI); |
| 221 | else |
| 222 | config_board_mux(MUX_TYPE_SDHC); |
| 223 | |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 224 | #if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_FSL_QSPI) |
Yuan Yao | 86f42d7 | 2016-06-08 18:24:57 +0800 | [diff] [blame] | 225 | val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4); |
| 226 | |
| 227 | if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3)) |
| 228 | QIXIS_WRITE(brdcfg[9], |
| 229 | (QIXIS_READ(brdcfg[9]) & 0xf8) | |
| 230 | FSL_QIXIS_BRDCFG9_QSPI); |
| 231 | #endif |
| 232 | |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 233 | #ifdef CONFIG_ENV_IS_NOWHERE |
| 234 | gd->env_addr = (ulong)&default_environment[0]; |
| 235 | #endif |
| 236 | select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); |
Chuanhua Han | 1ab68c7 | 2019-07-26 19:24:01 +0800 | [diff] [blame] | 237 | |
Chuanhua Han | 4f97aac | 2019-07-26 19:24:00 +0800 | [diff] [blame] | 238 | #ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT |
Chuanhua Han | 1ab68c7 | 2019-07-26 19:24:01 +0800 | [diff] [blame] | 239 | #ifdef CONFIG_DM_I2C |
| 240 | rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR); |
| 241 | #else |
Priyanka Jain | 2657e43 | 2015-06-29 15:39:40 +0530 | [diff] [blame] | 242 | rtc_enable_32khz_output(); |
Chuanhua Han | 4f97aac | 2019-07-26 19:24:00 +0800 | [diff] [blame] | 243 | #endif |
Chuanhua Han | 1ab68c7 | 2019-07-26 19:24:01 +0800 | [diff] [blame] | 244 | #endif |
| 245 | |
Udit Agarwal | c83ea8a | 2017-08-16 07:13:29 -0400 | [diff] [blame] | 246 | #ifdef CONFIG_FSL_CAAM |
| 247 | sec_init(); |
| 248 | #endif |
Santan Kumar | c61c699 | 2017-03-07 11:21:03 +0530 | [diff] [blame] | 249 | |
| 250 | #ifdef CONFIG_FSL_LS_PPA |
| 251 | ppa_init(); |
| 252 | #endif |
| 253 | |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 254 | return 0; |
| 255 | } |
| 256 | |
| 257 | int board_early_init_f(void) |
| 258 | { |
Yuan Yao | 5a89cce | 2016-06-08 18:24:54 +0800 | [diff] [blame] | 259 | #ifdef CONFIG_SYS_I2C_EARLY_INIT |
| 260 | i2c_early_init_f(); |
| 261 | #endif |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 262 | fsl_lsch3_early_init_f(); |
Yuan Yao | 2ec8584 | 2016-06-08 18:24:52 +0800 | [diff] [blame] | 263 | #ifdef CONFIG_FSL_QSPI |
| 264 | /* input clk: 1/2 platform clk, output: input/20 */ |
| 265 | out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20); |
| 266 | #endif |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 267 | return 0; |
| 268 | } |
| 269 | |
Priyanka Jain | 53e7ec0 | 2017-01-19 11:12:28 +0530 | [diff] [blame] | 270 | int misc_init_r(void) |
| 271 | { |
| 272 | if (adjust_vdd(0)) |
| 273 | printf("Warning: Adjusting core voltage failed.\n"); |
| 274 | |
| 275 | return 0; |
| 276 | } |
| 277 | |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 278 | void detail_board_ddr_info(void) |
| 279 | { |
| 280 | puts("\nDDR "); |
| 281 | print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); |
| 282 | print_ddr_info(0); |
Prabhakar Kushwaha | 122bcfd | 2015-11-09 16:42:07 +0530 | [diff] [blame] | 283 | #ifdef CONFIG_SYS_FSL_HAS_DP_DDR |
York Sun | cbe8e1c | 2016-04-04 11:41:26 -0700 | [diff] [blame] | 284 | if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 285 | puts("\nDP-DDR "); |
| 286 | print_size(gd->bd->bi_dram[2].size, ""); |
| 287 | print_ddr_info(CONFIG_DP_DDR_CTRL); |
| 288 | } |
Prabhakar Kushwaha | 122bcfd | 2015-11-09 16:42:07 +0530 | [diff] [blame] | 289 | #endif |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 290 | } |
| 291 | |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 292 | #if defined(CONFIG_ARCH_MISC_INIT) |
| 293 | int arch_misc_init(void) |
| 294 | { |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 295 | return 0; |
| 296 | } |
| 297 | #endif |
| 298 | |
Santan Kumar | 1afa900 | 2017-05-05 15:42:29 +0530 | [diff] [blame] | 299 | #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 300 | void fdt_fixup_board_enet(void *fdt) |
| 301 | { |
| 302 | int offset; |
| 303 | |
Stuart Yoder | a346615 | 2016-03-02 16:37:13 -0600 | [diff] [blame] | 304 | offset = fdt_path_offset(fdt, "/soc/fsl-mc"); |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 305 | |
| 306 | if (offset < 0) |
Stuart Yoder | a346615 | 2016-03-02 16:37:13 -0600 | [diff] [blame] | 307 | offset = fdt_path_offset(fdt, "/fsl-mc"); |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 308 | |
| 309 | if (offset < 0) { |
| 310 | printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", |
| 311 | __func__, offset); |
| 312 | return; |
| 313 | } |
| 314 | |
Mian Yousaf Kaukab | 9712465 | 2018-12-18 14:01:17 +0100 | [diff] [blame] | 315 | if (get_mc_boot_status() == 0 && |
| 316 | (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 317 | fdt_status_okay(fdt, offset); |
| 318 | else |
| 319 | fdt_status_fail(fdt, offset); |
| 320 | } |
Alexander Graf | 2ebeb44 | 2016-11-17 01:02:57 +0100 | [diff] [blame] | 321 | |
| 322 | void board_quiesce_devices(void) |
| 323 | { |
| 324 | fsl_mc_ldpaa_exit(gd->bd); |
| 325 | } |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 326 | #endif |
| 327 | |
| 328 | #ifdef CONFIG_OF_BOARD_SETUP |
| 329 | int ft_board_setup(void *blob, bd_t *bd) |
| 330 | { |
Bhupesh Sharma | 0b10a1a | 2015-05-28 14:54:10 +0530 | [diff] [blame] | 331 | u64 base[CONFIG_NR_DRAM_BANKS]; |
| 332 | u64 size[CONFIG_NR_DRAM_BANKS]; |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 333 | |
| 334 | ft_cpu_setup(blob, bd); |
| 335 | |
Bhupesh Sharma | 0b10a1a | 2015-05-28 14:54:10 +0530 | [diff] [blame] | 336 | /* fixup DT for the two GPP DDR banks */ |
| 337 | base[0] = gd->bd->bi_dram[0].start; |
| 338 | size[0] = gd->bd->bi_dram[0].size; |
| 339 | base[1] = gd->bd->bi_dram[1].start; |
| 340 | size[1] = gd->bd->bi_dram[1].size; |
| 341 | |
York Sun | 4de24ef | 2017-03-06 09:02:28 -0800 | [diff] [blame] | 342 | #ifdef CONFIG_RESV_RAM |
| 343 | /* reduce size if reserved memory is within this bank */ |
| 344 | if (gd->arch.resv_ram >= base[0] && |
| 345 | gd->arch.resv_ram < base[0] + size[0]) |
| 346 | size[0] = gd->arch.resv_ram - base[0]; |
| 347 | else if (gd->arch.resv_ram >= base[1] && |
| 348 | gd->arch.resv_ram < base[1] + size[1]) |
| 349 | size[1] = gd->arch.resv_ram - base[1]; |
| 350 | #endif |
| 351 | |
Bhupesh Sharma | 0b10a1a | 2015-05-28 14:54:10 +0530 | [diff] [blame] | 352 | fdt_fixup_memory_banks(blob, base, size, 2); |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 353 | |
Nipun Gupta | d691264 | 2018-08-20 16:01:14 +0530 | [diff] [blame] | 354 | fdt_fsl_mc_fixup_iommu_map_entry(blob); |
| 355 | |
Sriram Dash | 9fd465c | 2016-09-16 17:12:15 +0530 | [diff] [blame] | 356 | fsl_fdt_fixup_dr_usb(blob, bd); |
Sriram Dash | 0182095 | 2016-06-13 09:58:36 +0530 | [diff] [blame] | 357 | |
Santan Kumar | 1afa900 | 2017-05-05 15:42:29 +0530 | [diff] [blame] | 358 | #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 359 | fdt_fixup_board_enet(blob); |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 360 | #endif |
| 361 | |
Laurentiu Tudor | 4adff39 | 2019-10-18 09:01:54 +0000 | [diff] [blame] | 362 | fdt_fixup_icid(blob); |
| 363 | |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 364 | return 0; |
| 365 | } |
| 366 | #endif |
| 367 | |
| 368 | void qixis_dump_switch(void) |
| 369 | { |
| 370 | int i, nr_of_cfgsw; |
| 371 | |
| 372 | QIXIS_WRITE(cms[0], 0x00); |
| 373 | nr_of_cfgsw = QIXIS_READ(cms[1]); |
| 374 | |
| 375 | puts("DIP switch settings dump:\n"); |
| 376 | for (i = 1; i <= nr_of_cfgsw; i++) { |
| 377 | QIXIS_WRITE(cms[0], i); |
| 378 | printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); |
| 379 | } |
| 380 | } |