Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 1b7028d44fc3eaabf279e70a13343457851586f9 / . / board / Seagate / nas220 / nas220.c
blob: 1e6c43b1fabfa08f7a4255bbb9556c675653b78e [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Evgeni Dobreve80958b2014-12-08 17:49:42 +0100[diff] [blame]2/*
3 * Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
4 *
5 * Based on sheevaplug.c originally written by
6 * Prafulla Wadaskar <prafulla@marvell.com>
7 * (C) Copyright 2009
8 * Marvell Semiconductor <www.marvell.com>
Evgeni Dobreve80958b2014-12-08 17:49:42 +0100[diff] [blame]9 */
10
11#include <common.h>
12#include <miiphy.h>
Simon Glass0ffb9d62017-05-31 19:47:48 -0600[diff] [blame]13#include <asm/mach-types.h>
Evgeni Dobreve80958b2014-12-08 17:49:42 +0100[diff] [blame]14#include <asm/arch/soc.h>
15#include <asm/arch/mpp.h>
16#include <asm/arch/cpu.h>
17#include <asm/io.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
21int board_early_init_f(void)
22{
23 /*
24 * default gpio configuration
25 */
26 mvebu_config_gpio(NAS220_GE_OE_VAL_LOW, NAS220_GE_OE_VAL_HIGH,
27 NAS220_GE_OE_LOW, NAS220_GE_OE_HIGH);
28
29 /* Multi-Purpose Pins Functionality configuration */
30 static const u32 kwmpp_config[] = {
31 MPP0_NF_IO2,
32 MPP1_NF_IO3,
33 MPP2_NF_IO4,
34 MPP3_NF_IO5,
35 MPP4_NF_IO6,
36 MPP5_NF_IO7,
37 MPP6_SYSRST_OUTn,
38 MPP7_SPI_SCn,
39 MPP8_TW_SDA,
40 MPP9_TW_SCK,
41 MPP10_UART0_TXD,
42 MPP11_UART0_RXD,
43 MPP12_GPO,
44 MPP13_GPIO,
45 MPP14_GPIO,
46 MPP15_SATA0_ACTn,
47 MPP16_SATA1_ACTn,
48 MPP17_SATA0_PRESENTn,
49 MPP18_NF_IO0,
50 MPP19_NF_IO1,
51 MPP20_GPIO,
52 MPP21_GPIO,
53 MPP22_GPIO,
54 MPP23_GPIO,
55 MPP24_GPIO,
56 MPP25_GPIO,
57 MPP26_GPIO,
58 MPP27_GPIO,
59 MPP28_GPIO,
60 MPP29_GPIO,
61 MPP30_GPIO,
62 MPP31_GPIO,
63 MPP32_GPIO,
64 MPP33_GPIO,
65 MPP34_GPIO,
66 MPP35_GPIO,
67 0
68 };
69 kirkwood_mpp_conf(kwmpp_config, NULL);
70 return 0;
71}
72
73int board_init(void)
74{
75 /*
76 * arch number of board
77 */
Tom Rinid997f7c2017-01-25 20:42:36 -0500[diff] [blame]78 gd->bd->bi_arch_number = MACH_TYPE_RD88F6192_NAS;
Evgeni Dobreve80958b2014-12-08 17:49:42 +0100[diff] [blame]79
80 /* adress of boot parameters */
81 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
82
83 return 0;
84}
85
86#ifdef CONFIG_RESET_PHY_R
87/* Configure and enable MV88E1116 PHY */
88void reset_phy(void)
89{
90 u16 reg;
91 u16 devadr;
92 char *name = "egiga0";
93
94 if (miiphy_set_current_dev(name))
95 return;
96
97 /* command to read PHY dev address */
98 if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
99 printf("Err..%s could not read PHY dev address\n", __func__);
100 return;
101 }
102
103 /*
104 * Enable RGMII delay on Tx and Rx for CPU port
105 * Ref: sec 4.7.2 of chip datasheet
106 */
107 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
108 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
109 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
110 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
111 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
112
113 /* reset the phy */
114 miiphy_reset(name, devadr);
115
116 printf("88E1116 Initialized on %s\n", name);
117}
118#endif /* CONFIG_RESET_PHY_R */