Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Simon Glass | dc926ed | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 2 | /* |
3 | * Copyright (C) 2016 Google, Inc | ||||
4 | * Written by Simon Glass <sjg@chromium.org> | ||||
Simon Glass | dc926ed | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 5 | */ |
6 | |||||
7 | #include <config.h> | ||||
8 | |||||
Simon Glass | ff23e68 | 2019-05-02 10:52:20 -0600 | [diff] [blame] | 9 | #ifdef CONFIG_CHROMEOS |
Simon Glass | dc926ed | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 10 | / { |
11 | binman { | ||||
Simon Glass | ff23e68 | 2019-05-02 10:52:20 -0600 | [diff] [blame] | 12 | multiple-images; |
13 | rom: rom { | ||||
14 | }; | ||||
15 | }; | ||||
16 | }; | ||||
17 | #else | ||||
18 | / { | ||||
19 | rom: binman { | ||||
20 | }; | ||||
21 | }; | ||||
22 | #endif | ||||
23 | |||||
24 | #ifdef CONFIG_ROM_SIZE | ||||
25 | &rom { | ||||
Simon Glass | 771f02f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 26 | filename = "u-boot.rom"; |
27 | end-at-4gb; | ||||
28 | sort-by-offset; | ||||
29 | pad-byte = <0xff>; | ||||
30 | size = <CONFIG_ROM_SIZE>; | ||||
Simon Glass | dc926ed | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 31 | #ifdef CONFIG_HAVE_INTEL_ME |
Simon Glass | 771f02f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 32 | intel-descriptor { |
33 | filename = CONFIG_FLASH_DESCRIPTOR_FILE; | ||||
34 | }; | ||||
35 | intel-me { | ||||
36 | filename = CONFIG_INTEL_ME_FILE; | ||||
37 | }; | ||||
Simon Glass | dc926ed | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 38 | #endif |
Simon Glass | f03c70d | 2019-05-02 10:52:19 -0600 | [diff] [blame] | 39 | #ifdef CONFIG_TPL |
Simon Glass | 3c4b98f | 2019-12-06 21:42:26 -0700 | [diff] [blame] | 40 | #ifdef CONFIG_HAVE_MICROCODE |
Simon Glass | 771f02f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 41 | u-boot-tpl-with-ucode-ptr { |
42 | offset = <CONFIG_TPL_TEXT_BASE>; | ||||
43 | }; | ||||
44 | u-boot-tpl-dtb { | ||||
45 | }; | ||||
Simon Glass | 3c4b98f | 2019-12-06 21:42:26 -0700 | [diff] [blame] | 46 | #endif |
Simon Glass | 79c8732 | 2019-12-06 21:42:33 -0700 | [diff] [blame] | 47 | spl { |
48 | type = "section"; | ||||
Simon Glass | 4d7a923 | 2019-12-06 21:42:30 -0700 | [diff] [blame] | 49 | offset = <CONFIG_X86_OFFSET_SPL>; |
Simon Glass | 79c8732 | 2019-12-06 21:42:33 -0700 | [diff] [blame] | 50 | u-boot-spl { |
51 | }; | ||||
52 | u-boot-spl-dtb { | ||||
53 | }; | ||||
Simon Glass | 771f02f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 54 | }; |
55 | u-boot { | ||||
Simon Glass | 79c8732 | 2019-12-06 21:42:33 -0700 | [diff] [blame] | 56 | type = "section"; |
Simon Glass | 20af0ff | 2019-12-06 21:42:29 -0700 | [diff] [blame] | 57 | offset = <CONFIG_X86_OFFSET_U_BOOT>; |
Simon Glass | 79c8732 | 2019-12-06 21:42:33 -0700 | [diff] [blame] | 58 | u-boot-nodtb { |
59 | }; | ||||
60 | u-boot-dtb { | ||||
61 | }; | ||||
Simon Glass | 771f02f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 62 | }; |
Simon Glass | f03c70d | 2019-05-02 10:52:19 -0600 | [diff] [blame] | 63 | #elif defined(CONFIG_SPL) |
Simon Glass | 771f02f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 64 | u-boot-spl-with-ucode-ptr { |
Simon Glass | 4d7a923 | 2019-12-06 21:42:30 -0700 | [diff] [blame] | 65 | offset = <CONFIG_X86_OFFSET_SPL>; |
Simon Glass | 771f02f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 66 | }; |
67 | u-boot-dtb-with-ucode2 { | ||||
68 | type = "u-boot-dtb-with-ucode"; | ||||
69 | }; | ||||
70 | u-boot { | ||||
Simon Glass | 20af0ff | 2019-12-06 21:42:29 -0700 | [diff] [blame] | 71 | offset = <CONFIG_X86_OFFSET_U_BOOT>; |
Simon Glass | 771f02f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 72 | }; |
Simon Glass | 46be3c6 | 2017-01-16 07:04:23 -0700 | [diff] [blame] | 73 | #else |
Simon Glass | 014c66f | 2019-12-06 21:42:32 -0700 | [diff] [blame] | 74 | # ifdef CONFIG_SPL |
75 | u-boot { | ||||
76 | offset = <CONFIG_SYS_TEXT_BASE>; | ||||
77 | }; | ||||
78 | # else | ||||
79 | /* If there is no SPL then we need to put microcode in U-Boot */ | ||||
Simon Glass | 771f02f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 80 | u-boot-with-ucode-ptr { |
Simon Glass | 20af0ff | 2019-12-06 21:42:29 -0700 | [diff] [blame] | 81 | offset = <CONFIG_X86_OFFSET_U_BOOT>; |
Simon Glass | 771f02f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 82 | }; |
Simon Glass | 014c66f | 2019-12-06 21:42:32 -0700 | [diff] [blame] | 83 | # endif |
Simon Glass | 46be3c6 | 2017-01-16 07:04:23 -0700 | [diff] [blame] | 84 | #endif |
Simon Glass | 3c4b98f | 2019-12-06 21:42:26 -0700 | [diff] [blame] | 85 | #ifdef CONFIG_HAVE_MICROCODE |
Simon Glass | 771f02f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 86 | u-boot-dtb-with-ucode { |
87 | }; | ||||
88 | u-boot-ucode { | ||||
89 | align = <16>; | ||||
90 | }; | ||||
Simon Glass | 3c4b98f | 2019-12-06 21:42:26 -0700 | [diff] [blame] | 91 | #else |
92 | u-boot-dtb { | ||||
93 | }; | ||||
94 | #endif | ||||
Simon Glass | 7dbabbb | 2019-12-06 21:42:24 -0700 | [diff] [blame] | 95 | #ifdef CONFIG_HAVE_X86_FIT |
96 | intel-fit { | ||||
97 | }; | ||||
98 | intel-fit-ptr { | ||||
99 | }; | ||||
100 | #endif | ||||
Simon Glass | dc926ed | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 101 | #ifdef CONFIG_HAVE_MRC |
Simon Glass | 771f02f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 102 | intel-mrc { |
103 | offset = <CONFIG_X86_MRC_ADDR>; | ||||
104 | }; | ||||
Simon Glass | dc926ed | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 105 | #endif |
Simon Glass | f8dc7f4 | 2019-12-06 21:42:28 -0700 | [diff] [blame] | 106 | #ifdef CONFIG_FSP_VERSION1 |
Simon Glass | 771f02f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 107 | intel-fsp { |
108 | filename = CONFIG_FSP_FILE; | ||||
109 | offset = <CONFIG_FSP_ADDR>; | ||||
110 | }; | ||||
Simon Glass | dc926ed | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 111 | #endif |
Simon Glass | f8dc7f4 | 2019-12-06 21:42:28 -0700 | [diff] [blame] | 112 | #ifdef CONFIG_FSP_VERSION2 |
113 | intel-descriptor { | ||||
114 | filename = CONFIG_FLASH_DESCRIPTOR_FILE; | ||||
115 | }; | ||||
116 | intel-ifwi { | ||||
117 | filename = CONFIG_IFWI_INPUT_FILE; | ||||
118 | convert-fit; | ||||
119 | |||||
120 | section { | ||||
121 | size = <0x8000>; | ||||
122 | ifwi-replace; | ||||
123 | ifwi-subpart = "IBBP"; | ||||
124 | ifwi-entry = "IBBL"; | ||||
125 | u-boot-tpl { | ||||
126 | }; | ||||
127 | x86-start16-tpl { | ||||
128 | offset = <0x7800>; | ||||
129 | }; | ||||
130 | x86-reset16-tpl { | ||||
131 | offset = <0x7ff0>; | ||||
132 | }; | ||||
133 | }; | ||||
134 | }; | ||||
135 | intel-fsp-m { | ||||
136 | filename = CONFIG_FSP_FILE_M; | ||||
137 | }; | ||||
138 | intel-fsp-s { | ||||
139 | filename = CONFIG_FSP_FILE_S; | ||||
140 | }; | ||||
141 | #endif | ||||
Simon Glass | 8d54388 | 2019-12-06 21:42:31 -0700 | [diff] [blame] | 142 | fdtmap { |
143 | }; | ||||
Simon Glass | dc926ed | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 144 | #ifdef CONFIG_HAVE_CMC |
Simon Glass | 771f02f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 145 | intel-cmc { |
146 | filename = CONFIG_CMC_FILE; | ||||
147 | offset = <CONFIG_CMC_ADDR>; | ||||
148 | }; | ||||
Simon Glass | dc926ed | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 149 | #endif |
150 | #ifdef CONFIG_HAVE_VGA_BIOS | ||||
Simon Glass | 771f02f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 151 | intel-vga { |
152 | filename = CONFIG_VGA_BIOS_FILE; | ||||
153 | offset = <CONFIG_VGA_BIOS_ADDR>; | ||||
154 | }; | ||||
Simon Glass | dc926ed | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 155 | #endif |
Bin Meng | a3dd11a | 2017-08-15 22:41:55 -0700 | [diff] [blame] | 156 | #ifdef CONFIG_HAVE_VBT |
Simon Glass | 771f02f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 157 | intel-vbt { |
158 | filename = CONFIG_VBT_FILE; | ||||
159 | offset = <CONFIG_VBT_ADDR>; | ||||
160 | }; | ||||
Bin Meng | a3dd11a | 2017-08-15 22:41:55 -0700 | [diff] [blame] | 161 | #endif |
Simon Glass | dc926ed | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 162 | #ifdef CONFIG_HAVE_REFCODE |
Simon Glass | 771f02f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 163 | intel-refcode { |
164 | offset = <CONFIG_X86_REFCODE_ADDR>; | ||||
165 | }; | ||||
Simon Glass | dc926ed | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 166 | #endif |
Simon Glass | f03c70d | 2019-05-02 10:52:19 -0600 | [diff] [blame] | 167 | #ifdef CONFIG_TPL |
Simon Glass | 771f02f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 168 | x86-start16-tpl { |
169 | offset = <CONFIG_SYS_X86_START16>; | ||||
170 | }; | ||||
Simon Glass | abab18c | 2019-08-24 07:22:49 -0600 | [diff] [blame] | 171 | x86-reset16-tpl { |
172 | offset = <CONFIG_RESET_VEC_LOC>; | ||||
173 | }; | ||||
Simon Glass | f03c70d | 2019-05-02 10:52:19 -0600 | [diff] [blame] | 174 | #elif defined(CONFIG_SPL) |
Simon Glass | 771f02f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 175 | x86-start16-spl { |
176 | offset = <CONFIG_SYS_X86_START16>; | ||||
177 | }; | ||||
Simon Glass | abab18c | 2019-08-24 07:22:49 -0600 | [diff] [blame] | 178 | x86-reset16-spl { |
179 | offset = <CONFIG_RESET_VEC_LOC>; | ||||
180 | }; | ||||
Simon Glass | 46be3c6 | 2017-01-16 07:04:23 -0700 | [diff] [blame] | 181 | #else |
Simon Glass | 771f02f | 2019-05-02 10:52:21 -0600 | [diff] [blame] | 182 | x86-start16 { |
183 | offset = <CONFIG_SYS_X86_START16>; | ||||
184 | }; | ||||
Simon Glass | abab18c | 2019-08-24 07:22:49 -0600 | [diff] [blame] | 185 | x86-reset16 { |
186 | offset = <CONFIG_RESET_VEC_LOC>; | ||||
187 | }; | ||||
Simon Glass | 46be3c6 | 2017-01-16 07:04:23 -0700 | [diff] [blame] | 188 | #endif |
Simon Glass | 8d54388 | 2019-12-06 21:42:31 -0700 | [diff] [blame] | 189 | image-header { |
190 | location = "end"; | ||||
191 | }; | ||||
Simon Glass | dc926ed | 2016-11-25 20:16:02 -0700 | [diff] [blame] | 192 | }; |
193 | #endif |