blob: 4aafeed188101a6d6f90bc5450a985fba3ff6d8f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Adrian Alonso2b3d9612015-09-02 13:54:19 -05002/*
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
Adrian Alonso2b3d9612015-09-02 13:54:19 -05004 */
5
6#include <common.h>
7#include <asm/io.h>
8#include <asm/arch/imx-regs.h>
9#include <asm/arch/clock.h>
10#include <asm/arch/sys_proto.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020011#include <asm/mach-imx/dma.h>
12#include <asm/mach-imx/hab.h>
13#include <asm/mach-imx/rdc-sema.h>
Peng Fan47842492016-01-28 16:55:09 +080014#include <asm/arch/imx-rdc.h>
Adrian Alonso2b3d9612015-09-02 13:54:19 -050015#include <asm/arch/crm_regs.h>
16#include <dm.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060017#include <env.h>
Adrian Alonso2b3d9612015-09-02 13:54:19 -050018#include <imx_thermal.h>
Bryan O'Donoghue1ec9d9d2018-01-26 16:27:58 +000019#include <fsl_sec.h>
Bryan O'Donoghue0cdded82018-03-26 15:27:32 +010020#include <asm/setup.h>
Adrian Alonso2b3d9612015-09-02 13:54:19 -050021
Anson Huang9d618542018-08-08 09:17:49 +080022#define IOMUXC_GPR1 0x4
23#define BM_IOMUXC_GPR1_IRQ 0x1000
24
25#define GPC_LPCR_A7_BSC 0x0
26#define GPC_LPCR_M4 0x8
27#define GPC_SLPCR 0x14
28#define GPC_PGC_ACK_SEL_A7 0x24
29#define GPC_IMR1_CORE0 0x30
30#define GPC_IMR1_CORE1 0x40
31#define GPC_IMR1_M4 0x50
32#define GPC_PGC_CPU_MAPPING 0xec
33#define GPC_PGC_C0_PUPSCR 0x804
34#define GPC_PGC_SCU_TIMING 0x890
35#define GPC_PGC_C1_PUPSCR 0x844
36
37#define BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP 0x70000000
38#define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000
39#define BM_LPCR_M4_MASK_DSM_TRIGGER 0x80000000
40#define BM_SLPCR_EN_DSM 0x80000000
41#define BM_SLPCR_RBC_EN 0x40000000
42#define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000
43#define BM_SLPCR_VSTBY 0x4
44#define BM_SLPCR_SBYOS 0x2
45#define BM_SLPCR_BYPASS_PMIC_READY 0x1
46#define BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE 0x10000
47
48#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK 0x80000000
49#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK 0x8000
50
51#define BM_GPC_PGC_CORE_PUPSCR 0x7fff80
52
Adrian Alonso2b3d9612015-09-02 13:54:19 -050053#if defined(CONFIG_IMX_THERMAL)
54static const struct imx_thermal_plat imx7_thermal_plat = {
55 .regs = (void *)ANATOP_BASE_ADDR,
56 .fuse_bank = 3,
57 .fuse_word = 3,
58};
59
60U_BOOT_DEVICE(imx7_thermal) = {
61 .name = "imx_thermal",
62 .platdata = &imx7_thermal_plat,
63};
64#endif
65
Peng Fan77d3aeb2017-08-12 22:10:57 +080066#if CONFIG_IS_ENABLED(IMX_RDC)
Peng Fan47842492016-01-28 16:55:09 +080067/*
68 * In current design, if any peripheral was assigned to both A7 and M4,
69 * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
70 * low power mode. So M4 sleep will cause some peripherals fail to work
71 * at A7 core side. At default, all resources are in domain 0 - 3.
72 *
73 * There are 26 peripherals impacted by this IC issue:
74 * SIM2(sim2/emvsim2)
75 * SIM1(sim1/emvsim1)
76 * UART1/UART2/UART3/UART4/UART5/UART6/UART7
77 * SAI1/SAI2/SAI3
78 * WDOG1/WDOG2/WDOG3/WDOG4
79 * GPT1/GPT2/GPT3/GPT4
80 * PWM1/PWM2/PWM3/PWM4
81 * ENET1/ENET2
82 * Software Workaround:
83 * Here we setup some resources to domain 0 where M4 codes will move
84 * the M4 out of this domain. Then M4 is not able to access them any longer.
85 * This is a workaround for ic issue. So the peripherals are not shared
86 * by them. This way requires the uboot implemented the RDC driver and
87 * set the 26 IPs above to domain 0 only. M4 code will assign resource
88 * to its own domain, if it want to use the resource.
89 */
90static rdc_peri_cfg_t const resources[] = {
91 (RDC_PER_SIM1 | RDC_DOMAIN(0)),
92 (RDC_PER_SIM2 | RDC_DOMAIN(0)),
93 (RDC_PER_UART1 | RDC_DOMAIN(0)),
94 (RDC_PER_UART2 | RDC_DOMAIN(0)),
95 (RDC_PER_UART3 | RDC_DOMAIN(0)),
96 (RDC_PER_UART4 | RDC_DOMAIN(0)),
97 (RDC_PER_UART5 | RDC_DOMAIN(0)),
98 (RDC_PER_UART6 | RDC_DOMAIN(0)),
99 (RDC_PER_UART7 | RDC_DOMAIN(0)),
100 (RDC_PER_SAI1 | RDC_DOMAIN(0)),
101 (RDC_PER_SAI2 | RDC_DOMAIN(0)),
102 (RDC_PER_SAI3 | RDC_DOMAIN(0)),
103 (RDC_PER_WDOG1 | RDC_DOMAIN(0)),
104 (RDC_PER_WDOG2 | RDC_DOMAIN(0)),
105 (RDC_PER_WDOG3 | RDC_DOMAIN(0)),
106 (RDC_PER_WDOG4 | RDC_DOMAIN(0)),
107 (RDC_PER_GPT1 | RDC_DOMAIN(0)),
108 (RDC_PER_GPT2 | RDC_DOMAIN(0)),
109 (RDC_PER_GPT3 | RDC_DOMAIN(0)),
110 (RDC_PER_GPT4 | RDC_DOMAIN(0)),
111 (RDC_PER_PWM1 | RDC_DOMAIN(0)),
112 (RDC_PER_PWM2 | RDC_DOMAIN(0)),
113 (RDC_PER_PWM3 | RDC_DOMAIN(0)),
114 (RDC_PER_PWM4 | RDC_DOMAIN(0)),
115 (RDC_PER_ENET1 | RDC_DOMAIN(0)),
116 (RDC_PER_ENET2 | RDC_DOMAIN(0)),
117};
118
119static void isolate_resource(void)
120{
121 imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
122}
123#endif
124
Stefano Babicf8b509b2019-09-20 08:47:53 +0200125#if defined(CONFIG_IMX_HAB)
Adrian Alonsofcc8cb32015-10-12 13:48:13 -0500126struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
127 .bank = 1,
128 .word = 3,
129};
130#endif
131
Fabio Estevamf6ced1b2016-02-28 12:33:17 -0300132static bool is_mx7d(void)
133{
134 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
135 struct fuse_bank *bank = &ocotp->bank[1];
136 struct fuse_bank1_regs *fuse =
137 (struct fuse_bank1_regs *)bank->fuse_regs;
138 int val;
139
140 val = readl(&fuse->tester4);
141 if (val & 1)
142 return false;
143 else
144 return true;
145}
146
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500147u32 get_cpu_rev(void)
148{
149 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
150 ANATOP_BASE_ADDR;
151 u32 reg = readl(&ccm_anatop->digprog);
152 u32 type = (reg >> 16) & 0xff;
153
Fabio Estevamf6ced1b2016-02-28 12:33:17 -0300154 if (!is_mx7d())
155 type = MXC_CPU_MX7S;
156
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500157 reg &= 0xff;
158 return (type << 12) | reg;
159}
160
161#ifdef CONFIG_REVISION_TAG
162u32 __weak get_board_rev(void)
163{
164 return get_cpu_rev();
165}
166#endif
167
Peng Faneb518d52016-01-04 13:16:41 +0800168static void imx_enet_mdio_fixup(void)
169{
170 struct iomuxc_gpr_base_regs *gpr_regs =
171 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
172
173 /*
174 * The management data input/output (MDIO) requires open-drain,
175 * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
176 * this feature. So to TO1.1, need to enable open drain by setting
177 * bits GPR0[8:7].
178 */
179
180 if (soc_rev() >= CHIP_REV_1_1) {
181 setbits_le32(&gpr_regs->gpr[0],
182 IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
183 }
184}
185
Jun Nie9b1c85a2019-05-08 14:38:30 +0800186static void init_cpu_basic(void)
187{
188 imx_enet_mdio_fixup();
189
190#ifdef CONFIG_APBH_DMA
191 /* Start APBH DMA */
192 mxs_dma_init();
193#endif
194}
195
Igor Opaniukb65af982019-12-30 13:56:44 +0200196#ifdef CONFIG_IMX_BOOTAUX
197/*
198 * Table of mappings of physical mem regions in both
199 * Cortex-A7 and Cortex-M4 address spaces.
200 *
201 * For additional details check sections 2.1.2 and 2.1.3 in
202 * i.MX7Dual Applications Processor Reference Manual
203 *
204 */
205const struct rproc_att hostmap[] = {
206 /* aux core , host core, size */
207 { 0x00000000, 0x00180000, 0x8000 }, /* OCRAM_S */
208 { 0x00180000, 0x00180000, 0x8000 }, /* OCRAM_S */
209 { 0x20180000, 0x00180000, 0x8000 }, /* OCRAM_S */
210 { 0x1fff8000, 0x007f8000, 0x8000 }, /* TCML */
211 { 0x20000000, 0x00800000, 0x8000 }, /* TCMU */
212 { 0x00900000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
213 { 0x20200000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
214 { 0x00920000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
215 { 0x20220000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
216 { 0x00940000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
217 { 0x20240000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
218 { 0x10000000, 0x80000000, 0x0fff0000 }, /* DDR Code alias */
219 { 0x80000000, 0x80000000, 0xe0000000 }, /* DDRC */
220 { /* sentinel */ }
221};
222#endif
223
Jun Nie9b1c85a2019-05-08 14:38:30 +0800224#ifndef CONFIG_SKIP_LOWLEVEL_INIT
225/* enable all periherial can be accessed in nosec mode */
226static void init_csu(void)
227{
228 int i = 0;
229
230 for (i = 0; i < CSU_NUM_REGS; i++)
231 writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
232}
233
Anson Huang9d618542018-08-08 09:17:49 +0800234static void imx_gpcv2_init(void)
235{
236 u32 val, i;
237
238 /*
239 * Force IOMUXC irq pending, so that the interrupt to GPC can be
240 * used to deassert dsm_request signal when the signal gets
241 * asserted unexpectedly.
242 */
243 val = readl(IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
244 val |= BM_IOMUXC_GPR1_IRQ;
245 writel(val, IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
246
247 /* Initially mask all interrupts */
248 for (i = 0; i < 4; i++) {
249 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
250 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE1 + i * 4);
251 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_M4 + i * 4);
252 }
253
254 /* set SCU timing */
255 writel((0x59 << 10) | 0x5B | (0x2 << 20),
256 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING);
257
258 /* only external IRQs to wake up LPM and core 0/1 */
259 val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
260 val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP;
261 writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
262
263 /* set C0 power up timming per design requirement */
264 val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
265 val &= ~BM_GPC_PGC_CORE_PUPSCR;
266 val |= (0x1A << 7);
267 writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
268
269 /* set C1 power up timming per design requirement */
270 val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
271 val &= ~BM_GPC_PGC_CORE_PUPSCR;
272 val |= (0x1A << 7);
273 writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
274
275 /* dummy ack for time slot by default */
276 writel(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK |
277 BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK,
278 GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7);
279
280 /* mask M4 DSM trigger */
281 writel(readl(GPC_IPS_BASE_ADDR + GPC_LPCR_M4) |
282 BM_LPCR_M4_MASK_DSM_TRIGGER,
283 GPC_IPS_BASE_ADDR + GPC_LPCR_M4);
284
285 /* set mega/fast mix in A7 domain */
286 writel(0x1, GPC_IPS_BASE_ADDR + GPC_PGC_CPU_MAPPING);
287
288 /* DSM related settings */
289 val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
290 val &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN |
291 BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY |
292 BM_SLPCR_REG_BYPASS_COUNT);
293 val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE;
294 writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
295
296 /*
297 * disabling RBC need to delay at least 2 cycles of CKIL(32K)
298 * due to hardware design requirement, which is
299 * ~61us, here we use 65us for safe
300 */
301 udelay(65);
302}
303
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500304int arch_cpu_init(void)
305{
306 init_aips();
307
Peng Fanfcd53ce2015-10-23 10:13:04 +0800308 init_csu();
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500309 /* Disable PDE bit of WMCR register */
Fabio Estevam5f79d462017-11-23 10:55:33 -0200310 imx_wdog_disable_powerdown();
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500311
Jun Nie9b1c85a2019-05-08 14:38:30 +0800312 init_cpu_basic();
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500313
Peng Fan77d3aeb2017-08-12 22:10:57 +0800314#if CONFIG_IS_ENABLED(IMX_RDC)
315 isolate_resource();
316#endif
Peng Fan47842492016-01-28 16:55:09 +0800317
Bryan O'Donoghue0290ea02018-04-05 19:46:06 +0100318 init_snvs();
319
Anson Huang9d618542018-08-08 09:17:49 +0800320 imx_gpcv2_init();
321
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500322 return 0;
323}
Jun Nie9b1c85a2019-05-08 14:38:30 +0800324#else
325int arch_cpu_init(void)
326{
327 init_cpu_basic();
328
329 return 0;
330}
Rui Miguel Silvad1bb7a02018-09-05 11:56:05 +0100331#endif
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500332
Stefan Agner42dac202016-07-13 00:25:39 -0700333#ifdef CONFIG_ARCH_MISC_INIT
334int arch_misc_init(void)
335{
336#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
337 if (is_mx7d())
Simon Glass6a38e412017-08-03 12:22:09 -0600338 env_set("soc", "imx7d");
Stefan Agner42dac202016-07-13 00:25:39 -0700339 else
Simon Glass6a38e412017-08-03 12:22:09 -0600340 env_set("soc", "imx7s");
Stefan Agner42dac202016-07-13 00:25:39 -0700341#endif
342
Bryan O'Donoghue1ec9d9d2018-01-26 16:27:58 +0000343#ifdef CONFIG_FSL_CAAM
344 sec_init();
345#endif
346
Stefan Agner42dac202016-07-13 00:25:39 -0700347 return 0;
348}
349#endif
350
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500351#ifdef CONFIG_SERIAL_TAG
Bryan O'Donoghue3031d432018-03-26 15:27:33 +0100352/*
353 * OCOTP_TESTER
354 * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
355 * OCOTP_TESTER describes a unique ID based on silicon wafer
356 * and die X/Y position
357 *
358 * OCOTOP_TESTER offset 0x410
359 * 31:0 fuse 0
360 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
361 *
362 * OCOTP_TESTER1 offset 0x420
363 * 31:24 fuse 1
364 * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
365 * 23:16 fuse 1
366 * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
367 * 15:11 fuse 1
368 * The wafer number of the wafer on which the device was fabricated/SJC
369 * CHALLENGE/ Unique ID
370 * 10:0 fuse 1
371 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
372 */
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500373void get_board_serial(struct tag_serialnr *serialnr)
374{
375 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
376 struct fuse_bank *bank = &ocotp->bank[0];
377 struct fuse_bank0_regs *fuse =
378 (struct fuse_bank0_regs *)bank->fuse_regs;
379
380 serialnr->low = fuse->tester0;
381 serialnr->high = fuse->tester1;
382}
383#endif
384
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500385void set_wdog_reset(struct wdog_regs *wdog)
386{
387 u32 reg = readw(&wdog->wcr);
388 /*
389 * Output WDOG_B signal to reset external pmic or POR_B decided by
390 * the board desgin. Without external reset, the peripherals/DDR/
391 * PMIC are not reset, that may cause system working abnormal.
392 */
393 reg = readw(&wdog->wcr);
394 reg |= 1 << 3;
395 /*
396 * WDZST bit is write-once only bit. Align this bit in kernel,
397 * otherwise kernel code will have no chance to set this bit.
398 */
399 reg |= 1 << 0;
400 writew(reg, &wdog->wcr);
401}
402
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500403void s_init(void)
404{
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500405 /* clock configuration. */
406 clock_init();
407
408 return;
409}
Peng Fan99c874b2016-05-19 13:02:16 +0800410
411void reset_misc(void)
412{
Fabio Estevamad5fbe02018-12-11 16:40:37 -0200413#ifndef CONFIG_SPL_BUILD
Igor Opaniukf5abe402019-06-04 00:05:59 +0300414#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
Peng Fan99c874b2016-05-19 13:02:16 +0800415 lcdif_power_down();
416#endif
Fabio Estevamad5fbe02018-12-11 16:40:37 -0200417#endif
Peng Fan99c874b2016-05-19 13:02:16 +0800418}
419