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git01.mediatek.com / filogic / uboot / 1b695dbf7b87075420752fadf226cb2ec4a1082b / . / configs / T2080RDB_revD_SPIFLASH_defconfig
blob: 233ad4266021a1214b3dcadb294b5b69acd6a3a2 [file] [log] [blame]
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]1CONFIG_PPC=y
2CONFIG_SYS_TEXT_BASE=0x00201000
3CONFIG_SPL_LIBCOMMON_SUPPORT=y
4CONFIG_SPL_LIBGENERIC_SUPPORT=y
5CONFIG_SYS_MEMTEST_START=0x00200000
6CONFIG_SYS_MEMTEST_END=0x00400000
7CONFIG_ENV_SIZE=0x2000
8CONFIG_ENV_OFFSET=0x100000
9CONFIG_ENV_SECT_SIZE=0x10000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]10CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]11CONFIG_SPL_TEXT_BASE=0xFFFD8000
Simon Glassf4d60392021-08-08 12:20:12 -0600[diff] [blame]12CONFIG_SPL_SERIAL=y
Simon Glass284cb9c2021-07-10 21:14:31 -0600[diff] [blame]13CONFIG_SPL_DRIVERS_MISC=y
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]14CONFIG_SPL=y
15CONFIG_SPL_SPI_FLASH_SUPPORT=y
Simon Glassa5820472021-08-08 12:20:14 -0600[diff] [blame]16CONFIG_SPL_SPI=y
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]17CONFIG_MPC85xx=y
18CONFIG_TARGET_T2080RDB=y
19CONFIG_T2080RDB_REV_D=y
20CONFIG_FIT=y
21CONFIG_FIT_VERBOSE=y
22CONFIG_OF_BOARD_SETUP=y
23CONFIG_OF_STDOUT_VIA_ALIAS=y
Tom Rini9ff815a2021-08-24 23:11:49 -0400[diff] [blame]24CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
25CONFIG_RAMBOOT_PBL=y
26CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
27CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_spi_rcw.cfg"
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]28CONFIG_BOOTDELAY=10
Tom Rini5ddf1722021-11-10 09:11:40 -0500[diff] [blame]29CONFIG_USE_BOOTCOMMAND=y
30CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]31CONFIG_BOARD_EARLY_INIT_R=y
32# CONFIG_SPL_FRAMEWORK is not set
33CONFIG_SPL_SPI_BOOT=y
34CONFIG_SPL_FSL_PBL=y
35CONFIG_SPL_ENV_SUPPORT=y
Simon Glassbccfc2e2021-07-10 21:14:36 -0600[diff] [blame]36CONFIG_SPL_I2C=y
Simon Glass64571062021-08-08 12:20:16 -0600[diff] [blame]37CONFIG_SPL_MPC8XXX_INIT_DDR=y
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]38CONFIG_HUSH_PARSER=y
39CONFIG_CMD_IMLS=y
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]40CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]41CONFIG_CMD_MEMTEST=y
42CONFIG_SYS_ALT_MEMTEST=y
43CONFIG_CMD_DM=y
44CONFIG_CMD_I2C=y
45CONFIG_CMD_MMC=y
46CONFIG_CMD_USB=y
47CONFIG_CMD_DHCP=y
48CONFIG_CMD_MII=y
49CONFIG_CMD_PING=y
50CONFIG_MP=y
51CONFIG_CMD_EXT2=y
52CONFIG_CMD_FAT=y
53CONFIG_CMD_MTDPARTS=y
54CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
55CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
56# CONFIG_CMD_IRQ is not set
57CONFIG_OF_CONTROL=y
58CONFIG_ENV_OVERWRITE=y
59CONFIG_ENV_IS_IN_SPI_FLASH=y
60CONFIG_DM=y
61CONFIG_FSL_CAAM=y
Tom Rinif7246c22021-08-21 13:50:17 -0400[diff] [blame]62CONFIG_DDR_CLK_FREQ=133330000
Tom Rini468c2d52021-08-21 13:50:18 -0400[diff] [blame]63CONFIG_DDR_ECC=y
64CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]65CONFIG_DM_I2C=y
Tom Rini52b2e262021-08-18 23:12:24 -0400[diff] [blame]66CONFIG_SPL_SYS_I2C_LEGACY=y
Tom Rinib1b13072021-08-18 23:12:37 -0400[diff] [blame]67CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
Tom Rinibe94c762021-08-18 23:12:35 -0400[diff] [blame]68CONFIG_SYS_I2C_FSL=y
69CONFIG_SYS_FSL_I2C_OFFSET=0x118000
70CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
71CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
72CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
73CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
74CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
75CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]76CONFIG_SYS_I2C_EEPROM_ADDR=0x50
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]77CONFIG_FSL_ESDHC=y
78CONFIG_MTD=y
79CONFIG_MTD_NOR_FLASH=y
80CONFIG_FLASH_CFI_DRIVER=y
81CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
82CONFIG_FLASH_CFI_MTD=y
83CONFIG_SYS_FLASH_CFI=y
84CONFIG_DM_SPI_FLASH=y
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]85CONFIG_SF_DEFAULT_SPEED=10000000
86CONFIG_SPI_FLASH_STMICRO=y
87CONFIG_PHYLIB=y
88CONFIG_PHY_AQUANTIA=y
89CONFIG_PHY_CORTINA=y
90CONFIG_SYS_CORTINA_FW_IN_SPIFLASH=y
Kuldeep Singh016965f2021-08-10 11:20:07 +0530[diff] [blame]91CONFIG_CORTINA_FW_ADDR=0x120000
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]92CONFIG_PHY_REALTEK=y
93CONFIG_DM_ETH=y
94CONFIG_DM_MDIO=y
95CONFIG_E1000=y
96CONFIG_FMAN_ENET=y
Rajesh Bhagataec38012021-11-09 16:30:38 +0530[diff] [blame]97CONFIG_SYS_FMAN_FW_ADDR=0x110000
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]98CONFIG_MII=y
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]99CONFIG_DM_PCI_COMPAT=y
100CONFIG_PCIE_FSL=y
101CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
102CONFIG_DM_RTC=y
103CONFIG_RTC_DS1307=y
104CONFIG_SYS_NS16550=y
105CONFIG_SPI=y
106CONFIG_DM_SPI=y
107CONFIG_FSL_ESPI=y
108CONFIG_USB=y
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]109CONFIG_USB_STORAGE=y
110CONFIG_ADDR_MAP=y
111CONFIG_SYS_NUM_ADDR_MAP=64