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git01.mediatek.com / filogic / uboot / 1b64ffa0f87a26da733a948e9b7a6e06f09ba2b5 / . / arch / openrisc / lib / board.c
blob: b7fbd2f125305f21802a68f8a32be312fb33a7fe [file] [log] [blame]
Stefan Kristianssoncfbf96b2011-11-26 19:04:52 +0000[diff] [blame]1/*
2 * (C) Copyright 2011
3 * Julius Baxter, julius@opencores.org
4 *
5 * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
6 * Scott McNutt <smcnutt@psyent.com>
7 *
8 * (C) Copyright 2000-2002
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 *
11 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]12 * SPDX-License-Identifier: GPL-2.0+
Stefan Kristianssoncfbf96b2011-11-26 19:04:52 +0000[diff] [blame]13 */
14
15#include <common.h>
Bin Meng52d67602016-01-25 01:53:13 -0800[diff] [blame]16#include <console.h>
Stefan Kristianssoncfbf96b2011-11-26 19:04:52 +0000[diff] [blame]17#include <stdio_dev.h>
18#include <watchdog.h>
19#include <malloc.h>
20#include <mmc.h>
21#include <net.h>
22#ifdef CONFIG_STATUS_LED
23#include <status_led.h>
24#endif
25#ifdef CONFIG_CMD_NAND
26#include <nand.h> /* cannot even include nand.h if it isnt configured */
27#endif
28
29#include <timestamp.h>
30#include <version.h>
31
32DECLARE_GLOBAL_DATA_PTR;
33
34/*
35 * All attempts to come up with a "common" initialization sequence
36 * that works for all boards and architectures failed: some of the
37 * requirements are just _too_ different. To get rid of the resulting
38 * mess of board dependend #ifdef'ed code we now make the whole
39 * initialization sequence configurable to the user.
40 *
41 * The requirements for any new initalization function is simple: it
42 * receives a pointer to the "global data" structure as it's only
43 * argument, and returns an integer return code, where 0 means
44 * "continue" and != 0 means "fatal error, hang the system".
45 */
46
47extern int cache_init(void);
48
49/*
50 * Initialization sequence
51 */
52static int (* const init_sequence[])(void) = {
53 cache_init,
54 timer_init, /* initialize timer */
55 env_init,
56 serial_init,
57 console_init_f,
58 display_options,
59 checkcpu,
60 checkboard,
61};
62
63
64/***********************************************************************/
65void board_init(void)
66{
67 bd_t *bd;
68 int i;
69
70 gd = (gd_t *)CONFIG_SYS_GBL_DATA_ADDR;
71
72 memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
73
74 gd->bd = (bd_t *)(gd+1); /* At end of global data */
75 gd->baudrate = CONFIG_BAUDRATE;
76 gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
77
78 bd = gd->bd;
79 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
80 bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
81#ifndef CONFIG_SYS_NO_FLASH
82 bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
83#endif
84#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
85 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
86 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
87#endif
Stefan Kristianssoncfbf96b2011-11-26 19:04:52 +0000[diff] [blame]88
89 for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
90 WATCHDOG_RESET();
91 if (init_sequence[i]())
92 hang();
93 }
94
95 WATCHDOG_RESET();
96
97 /* The Malloc area is immediately below the monitor copy in RAM */
98 mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
99
100#ifndef CONFIG_SYS_NO_FLASH
101 WATCHDOG_RESET();
102 bd->bi_flashsize = flash_init();
103#endif
104
105#ifdef CONFIG_CMD_NAND
106 puts("NAND: ");
107 nand_init();
108#endif
109
110#ifdef CONFIG_GENERIC_MMC
111 puts("MMC: ");
112 mmc_initialize(bd);
113#endif
114
115 WATCHDOG_RESET();
116 env_relocate();
117
118 WATCHDOG_RESET();
119 stdio_init();
120 jumptable_init();
121 console_init_r();
122
123 WATCHDOG_RESET();
124 interrupt_init();
125
126#if defined(CONFIG_BOARD_LATE_INIT)
127 board_late_init();
128#endif
129
130#if defined(CONFIG_CMD_NET)
131 puts("NET: ");
Joe Hershberger3dbe17e2015-03-22 17:09:06 -0500[diff] [blame]132 eth_initialize();
Stefan Kristianssoncfbf96b2011-11-26 19:04:52 +0000[diff] [blame]133#endif
134
135 /* main_loop */
136 for (;;) {
137 WATCHDOG_RESET();
138 main_loop();
139 }
140}