Kever Yang | 5f94896 | 2017-06-23 17:17:50 +0800 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2017 Rockchip Electronics Co., Ltd. |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | #ifndef _ASM_ARCH_GRF_RK322X_H |
| 7 | #define _ASM_ARCH_GRF_RK322X_H |
| 8 | |
| 9 | #include <common.h> |
| 10 | |
| 11 | struct rk322x_grf { |
| 12 | unsigned int gpio0a_iomux; |
| 13 | unsigned int gpio0b_iomux; |
| 14 | unsigned int gpio0c_iomux; |
| 15 | unsigned int gpio0d_iomux; |
| 16 | |
| 17 | unsigned int gpio1a_iomux; |
| 18 | unsigned int gpio1b_iomux; |
| 19 | unsigned int gpio1c_iomux; |
| 20 | unsigned int gpio1d_iomux; |
| 21 | |
| 22 | unsigned int gpio2a_iomux; |
| 23 | unsigned int gpio2b_iomux; |
| 24 | unsigned int gpio2c_iomux; |
| 25 | unsigned int gpio2d_iomux; |
| 26 | |
| 27 | unsigned int gpio3a_iomux; |
| 28 | unsigned int gpio3b_iomux; |
| 29 | unsigned int gpio3c_iomux; |
| 30 | unsigned int gpio3d_iomux; |
| 31 | |
| 32 | unsigned int reserved1[4]; |
| 33 | unsigned int con_iomux; |
| 34 | unsigned int reserved2[(0x100 - 0x50) / 4 - 1]; |
| 35 | unsigned int gpio0_p[4]; |
| 36 | unsigned int gpio1_p[4]; |
| 37 | unsigned int gpio2_p[4]; |
| 38 | unsigned int gpio3_p[4]; |
| 39 | unsigned int reserved3[(0x200 - 0x13c) / 4 - 1]; |
| 40 | unsigned int gpio0_e[4]; |
| 41 | unsigned int gpio1_e[4]; |
| 42 | unsigned int gpio2_e[4]; |
| 43 | unsigned int gpio3_e[4]; |
| 44 | unsigned int reserved4[(0x400 - 0x23c) / 4 - 1]; |
| 45 | unsigned int soc_con[7]; |
| 46 | unsigned int reserved5[(0x480 - 0x418) / 4 - 1]; |
| 47 | unsigned int soc_status[3]; |
| 48 | unsigned int chip_id; |
| 49 | unsigned int reserved6[(0x500 - 0x48c) / 4 - 1]; |
| 50 | unsigned int cpu_con[4]; |
| 51 | unsigned int reserved7[4]; |
| 52 | unsigned int cpu_status[2]; |
| 53 | unsigned int reserved8[(0x5c8 - 0x524) / 4 - 1]; |
| 54 | unsigned int os_reg[8]; |
| 55 | unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1]; |
| 56 | unsigned int ddrc_stat; |
| 57 | }; |
| 58 | check_member(rk322x_grf, ddrc_stat, 0x604); |
| 59 | |
| 60 | struct rk322x_sgrf { |
| 61 | unsigned int soc_con[11]; |
| 62 | unsigned int busdmac_con[4]; |
| 63 | }; |
| 64 | |
| 65 | /* GRF_GPIO0A_IOMUX */ |
| 66 | enum { |
| 67 | GPIO0A7_SHIFT = 14, |
| 68 | GPIO0A7_MASK = 3 << GPIO0A7_SHIFT, |
| 69 | GPIO0A7_GPIO = 0, |
| 70 | GPIO0A7_I2C3_SDA, |
| 71 | GPIO0A7_HDMI_DDCSDA, |
| 72 | |
| 73 | GPIO0A6_SHIFT = 12, |
| 74 | GPIO0A6_MASK = 3 << GPIO0A6_SHIFT, |
| 75 | GPIO0A6_GPIO = 0, |
| 76 | GPIO0A6_I2C3_SCL, |
| 77 | GPIO0A6_HDMI_DDCSCL, |
| 78 | |
| 79 | GPIO0A3_SHIFT = 6, |
| 80 | GPIO0A3_MASK = 3 << GPIO0A3_SHIFT, |
| 81 | GPIO0A3_GPIO = 0, |
| 82 | GPIO0A3_I2C1_SDA, |
| 83 | GPIO0A3_SDIO_CMD, |
| 84 | |
| 85 | GPIO0A2_SHIFT = 4, |
| 86 | GPIO0A2_MASK = 3 << GPIO0A2_SHIFT, |
| 87 | GPIO0A2_GPIO = 0, |
| 88 | GPIO0A2_I2C1_SCL, |
| 89 | |
| 90 | GPIO0A1_SHIFT = 2, |
| 91 | GPIO0A1_MASK = 3 << GPIO0A1_SHIFT, |
| 92 | GPIO0A1_GPIO = 0, |
| 93 | GPIO0A1_I2C0_SDA, |
| 94 | |
| 95 | GPIO0A0_SHIFT = 0, |
| 96 | GPIO0A0_MASK = 3 << GPIO0A0_SHIFT, |
| 97 | GPIO0A0_GPIO = 0, |
| 98 | GPIO0A0_I2C0_SCL, |
| 99 | }; |
| 100 | |
| 101 | /* GRF_GPIO0B_IOMUX */ |
| 102 | enum { |
| 103 | GPIO0B7_SHIFT = 14, |
| 104 | GPIO0B7_MASK = 3 << GPIO0B7_SHIFT, |
| 105 | GPIO0B7_GPIO = 0, |
| 106 | GPIO0B7_HDMI_HDP, |
| 107 | |
| 108 | GPIO0B6_SHIFT = 12, |
| 109 | GPIO0B6_MASK = 3 << GPIO0B6_SHIFT, |
| 110 | GPIO0B6_GPIO = 0, |
| 111 | GPIO0B6_I2S_SDI, |
| 112 | GPIO0B6_SPI_CSN0, |
| 113 | |
| 114 | GPIO0B5_SHIFT = 10, |
| 115 | GPIO0B5_MASK = 3 << GPIO0B5_SHIFT, |
| 116 | GPIO0B5_GPIO = 0, |
| 117 | GPIO0B5_I2S_SDO, |
| 118 | GPIO0B5_SPI_RXD, |
| 119 | |
| 120 | GPIO0B3_SHIFT = 6, |
| 121 | GPIO0B3_MASK = 3 << GPIO0B3_SHIFT, |
| 122 | GPIO0B3_GPIO = 0, |
| 123 | GPIO0B3_I2S1_LRCKRX, |
| 124 | GPIO0B3_SPI_TXD, |
| 125 | |
| 126 | GPIO0B1_SHIFT = 2, |
| 127 | GPIO0B1_MASK = 3 << GPIO0B1_SHIFT, |
| 128 | GPIO0B1_GPIO = 0, |
| 129 | GPIO0B1_I2S_SCLK, |
| 130 | GPIO0B1_SPI_CLK, |
| 131 | |
| 132 | GPIO0B0_SHIFT = 0, |
| 133 | GPIO0B0_MASK = 3, |
| 134 | GPIO0B0_GPIO = 0, |
| 135 | GPIO0B0_I2S_MCLK, |
| 136 | }; |
| 137 | |
| 138 | /* GRF_GPIO0C_IOMUX */ |
| 139 | enum { |
| 140 | GPIO0C4_SHIFT = 8, |
| 141 | GPIO0C4_MASK = 3 << GPIO0C4_SHIFT, |
| 142 | GPIO0C4_GPIO = 0, |
| 143 | GPIO0C4_HDMI_CECSDA, |
| 144 | |
| 145 | GPIO0C1_SHIFT = 2, |
| 146 | GPIO0C1_MASK = 3 << GPIO0C1_SHIFT, |
| 147 | GPIO0C1_GPIO = 0, |
| 148 | GPIO0C1_UART0_RSTN, |
| 149 | GPIO0C1_CLK_OUT1, |
| 150 | }; |
| 151 | |
| 152 | /* GRF_GPIO0D_IOMUX */ |
| 153 | enum { |
| 154 | GPIO0D6_SHIFT = 12, |
| 155 | GPIO0D6_MASK = 3 << GPIO0D6_SHIFT, |
| 156 | GPIO0D6_GPIO = 0, |
| 157 | GPIO0D6_SDIO_PWREN, |
| 158 | GPIO0D6_PWM11, |
| 159 | |
| 160 | |
| 161 | GPIO0D4_SHIFT = 8, |
| 162 | GPIO0D4_MASK = 3 << GPIO0D4_SHIFT, |
| 163 | GPIO0D4_GPIO = 0, |
| 164 | GPIO0D4_PWM2, |
| 165 | |
| 166 | GPIO0D3_SHIFT = 6, |
| 167 | GPIO0D3_MASK = 3 << GPIO0D3_SHIFT, |
| 168 | GPIO0D3_GPIO = 0, |
| 169 | GPIO0D3_PWM1, |
| 170 | |
| 171 | GPIO0D2_SHIFT = 4, |
| 172 | GPIO0D2_MASK = 3 << GPIO0D2_SHIFT, |
| 173 | GPIO0D2_GPIO = 0, |
| 174 | GPIO0D2_PWM0, |
| 175 | }; |
| 176 | |
| 177 | /* GRF_GPIO1A_IOMUX */ |
| 178 | enum { |
| 179 | GPIO1A7_SHIFT = 14, |
| 180 | GPIO1A7_MASK = 1, |
| 181 | GPIO1A7_GPIO = 0, |
| 182 | GPIO1A7_SDMMC_WRPRT, |
| 183 | }; |
| 184 | |
| 185 | /* GRF_GPIO1B_IOMUX */ |
| 186 | enum { |
| 187 | GPIO1B7_SHIFT = 14, |
| 188 | GPIO1B7_MASK = 3 << GPIO1B7_SHIFT, |
| 189 | GPIO1B7_GPIO = 0, |
| 190 | GPIO1B7_SDMMC_CMD, |
| 191 | |
| 192 | GPIO1B6_SHIFT = 12, |
| 193 | GPIO1B6_MASK = 3 << GPIO1B6_SHIFT, |
| 194 | GPIO1B6_GPIO = 0, |
| 195 | GPIO1B6_SDMMC_PWREN, |
| 196 | |
| 197 | GPIO1B4_SHIFT = 8, |
| 198 | GPIO1B4_MASK = 3 << GPIO1B4_SHIFT, |
| 199 | GPIO1B4_GPIO = 0, |
| 200 | GPIO1B4_SPI_CSN1, |
| 201 | GPIO1B4_PWM12, |
| 202 | |
| 203 | GPIO1B3_SHIFT = 6, |
| 204 | GPIO1B3_MASK = 3 << GPIO1B3_SHIFT, |
| 205 | GPIO1B3_GPIO = 0, |
| 206 | GPIO1B3_UART1_RSTN, |
| 207 | GPIO1B3_PWM13, |
| 208 | |
| 209 | GPIO1B2_SHIFT = 4, |
| 210 | GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, |
| 211 | GPIO1B2_GPIO = 0, |
| 212 | GPIO1B2_UART1_SIN, |
| 213 | GPIO1B2_UART21_SIN, |
| 214 | |
| 215 | GPIO1B1_SHIFT = 2, |
| 216 | GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, |
| 217 | GPIO1B1_GPIO = 0, |
| 218 | GPIO1B1_UART1_SOUT, |
| 219 | GPIO1B1_UART21_SOUT, |
| 220 | }; |
| 221 | |
| 222 | /* GRF_GPIO1C_IOMUX */ |
| 223 | enum { |
| 224 | GPIO1C7_SHIFT = 14, |
| 225 | GPIO1C7_MASK = 3 << GPIO1C7_SHIFT, |
| 226 | GPIO1C7_GPIO = 0, |
| 227 | GPIO1C7_NAND_CS3, |
| 228 | GPIO1C7_EMMC_RSTNOUT, |
| 229 | |
| 230 | GPIO1C6_SHIFT = 12, |
| 231 | GPIO1C6_MASK = 3 << GPIO1C6_SHIFT, |
| 232 | GPIO1C6_GPIO = 0, |
| 233 | GPIO1C6_NAND_CS2, |
| 234 | GPIO1C6_EMMC_CMD, |
| 235 | |
| 236 | |
| 237 | GPIO1C5_SHIFT = 10, |
| 238 | GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, |
| 239 | GPIO1C5_GPIO = 0, |
| 240 | GPIO1C5_SDMMC_D3, |
| 241 | GPIO1C5_JTAG_TMS, |
| 242 | |
| 243 | GPIO1C4_SHIFT = 8, |
| 244 | GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, |
| 245 | GPIO1C4_GPIO = 0, |
| 246 | GPIO1C4_SDMMC_D2, |
| 247 | GPIO1C4_JTAG_TCK, |
| 248 | |
| 249 | GPIO1C3_SHIFT = 6, |
| 250 | GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, |
| 251 | GPIO1C3_GPIO = 0, |
| 252 | GPIO1C3_SDMMC_D1, |
| 253 | GPIO1C3_UART2_SIN, |
| 254 | |
| 255 | GPIO1C2_SHIFT = 4, |
| 256 | GPIO1C2_MASK = 3 << GPIO1C2_SHIFT , |
| 257 | GPIO1C2_GPIO = 0, |
| 258 | GPIO1C2_SDMMC_D0, |
| 259 | GPIO1C2_UART2_SOUT, |
| 260 | |
| 261 | GPIO1C1_SHIFT = 2, |
| 262 | GPIO1C1_MASK = 3 << GPIO1C1_SHIFT, |
| 263 | GPIO1C1_GPIO = 0, |
| 264 | GPIO1C1_SDMMC_DETN, |
| 265 | |
| 266 | GPIO1C0_SHIFT = 0, |
| 267 | GPIO1C0_MASK = 3 << GPIO1C0_SHIFT, |
| 268 | GPIO1C0_GPIO = 0, |
| 269 | GPIO1C0_SDMMC_CLKOUT, |
| 270 | }; |
| 271 | |
| 272 | /* GRF_GPIO1D_IOMUX */ |
| 273 | enum { |
| 274 | GPIO1D7_SHIFT = 14, |
| 275 | GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, |
| 276 | GPIO1D7_GPIO = 0, |
| 277 | GPIO1D7_NAND_D7, |
| 278 | GPIO1D7_EMMC_D7, |
| 279 | |
| 280 | GPIO1D6_SHIFT = 12, |
| 281 | GPIO1D6_MASK = 3 << GPIO1D6_SHIFT, |
| 282 | GPIO1D6_GPIO = 0, |
| 283 | GPIO1D6_NAND_D6, |
| 284 | GPIO1D6_EMMC_D6, |
| 285 | |
| 286 | GPIO1D5_SHIFT = 10, |
| 287 | GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, |
| 288 | GPIO1D5_GPIO = 0, |
| 289 | GPIO1D5_NAND_D5, |
| 290 | GPIO1D5_EMMC_D5, |
| 291 | |
| 292 | GPIO1D4_SHIFT = 8, |
| 293 | GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, |
| 294 | GPIO1D4_GPIO = 0, |
| 295 | GPIO1D4_NAND_D4, |
| 296 | GPIO1D4_EMMC_D4, |
| 297 | |
| 298 | GPIO1D3_SHIFT = 6, |
| 299 | GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, |
| 300 | GPIO1D3_GPIO = 0, |
| 301 | GPIO1D3_NAND_D3, |
| 302 | GPIO1D3_EMMC_D3, |
| 303 | |
| 304 | GPIO1D2_SHIFT = 4, |
| 305 | GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, |
| 306 | GPIO1D2_GPIO = 0, |
| 307 | GPIO1D2_NAND_D2, |
| 308 | GPIO1D2_EMMC_D2, |
| 309 | |
| 310 | GPIO1D1_SHIFT = 2, |
| 311 | GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, |
| 312 | GPIO1D1_GPIO = 0, |
| 313 | GPIO1D1_NAND_D1, |
| 314 | GPIO1D1_EMMC_D1, |
| 315 | |
| 316 | GPIO1D0_SHIFT = 0, |
| 317 | GPIO1D0_MASK = 3 << GPIO1D0_SHIFT, |
| 318 | GPIO1D0_GPIO = 0, |
| 319 | GPIO1D0_NAND_D0, |
| 320 | GPIO1D0_EMMC_D0, |
| 321 | }; |
| 322 | |
| 323 | /* GRF_GPIO2A_IOMUX */ |
| 324 | enum { |
| 325 | GPIO2A7_SHIFT = 14, |
| 326 | GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, |
| 327 | GPIO2A7_GPIO = 0, |
| 328 | GPIO2A7_NAND_DQS, |
| 329 | GPIO2A7_EMMC_CLKOUT, |
| 330 | |
| 331 | GPIO2A5_SHIFT = 10, |
| 332 | GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, |
| 333 | GPIO2A5_GPIO = 0, |
| 334 | GPIO2A5_NAND_WP, |
| 335 | GPIO2A5_EMMC_PWREN, |
| 336 | |
| 337 | GPIO2A4_SHIFT = 8, |
| 338 | GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, |
| 339 | GPIO2A4_GPIO = 0, |
| 340 | GPIO2A4_NAND_RDY, |
| 341 | GPIO2A4_EMMC_CMD, |
| 342 | |
| 343 | GPIO2A3_SHIFT = 6, |
| 344 | GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, |
| 345 | GPIO2A3_GPIO = 0, |
| 346 | GPIO2A3_NAND_RDN, |
| 347 | GPIO2A4_SPI1_CSN1, |
| 348 | |
| 349 | GPIO2A2_SHIFT = 4, |
| 350 | GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, |
| 351 | GPIO2A2_GPIO = 0, |
| 352 | GPIO2A2_NAND_WRN, |
| 353 | GPIO2A4_SPI1_CSN0, |
| 354 | |
| 355 | GPIO2A1_SHIFT = 2, |
| 356 | GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, |
| 357 | GPIO2A1_GPIO = 0, |
| 358 | GPIO2A1_NAND_CLE, |
| 359 | GPIO2A1_SPI1_TXD, |
| 360 | |
| 361 | GPIO2A0_SHIFT = 0, |
| 362 | GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, |
| 363 | GPIO2A0_GPIO = 0, |
| 364 | GPIO2A0_NAND_ALE, |
| 365 | GPIO2A0_SPI1_RXD, |
| 366 | }; |
| 367 | |
| 368 | /* GRF_GPIO2B_IOMUX */ |
| 369 | enum { |
| 370 | GPIO2B7_SHIFT = 14, |
| 371 | GPIO2B7_MASK = 3 << GPIO2B7_SHIFT, |
| 372 | GPIO2B7_GPIO = 0, |
| 373 | GPIO2B7_GMAC_RXER, |
| 374 | |
| 375 | GPIO2B6_SHIFT = 12, |
| 376 | GPIO2B6_MASK = 3 << GPIO2B6_SHIFT, |
| 377 | GPIO2B6_GPIO = 0, |
| 378 | GPIO2B6_GMAC_CLK, |
| 379 | GPIO2B6_MAC_LINK, |
| 380 | |
| 381 | GPIO2B5_SHIFT = 10, |
| 382 | GPIO2B5_MASK = 3 << GPIO2B5_SHIFT, |
| 383 | GPIO2B5_GPIO = 0, |
| 384 | GPIO2B5_GMAC_TXEN, |
| 385 | |
| 386 | GPIO2B4_SHIFT = 8, |
| 387 | GPIO2B4_MASK = 3 << GPIO2B4_SHIFT, |
| 388 | GPIO2B4_GPIO = 0, |
| 389 | GPIO2B4_GMAC_MDIO, |
| 390 | |
| 391 | GPIO2B3_SHIFT = 6, |
| 392 | GPIO2B3_MASK = 3 << GPIO2B3_SHIFT, |
| 393 | GPIO2B3_GPIO = 0, |
| 394 | GPIO2B3_GMAC_RXCLK, |
| 395 | |
| 396 | GPIO2B2_SHIFT = 4, |
| 397 | GPIO2B2_MASK = 3 << GPIO2B2_SHIFT, |
| 398 | GPIO2B2_GPIO = 0, |
| 399 | GPIO2B2_GMAC_CRS, |
| 400 | |
| 401 | GPIO2B1_SHIFT = 2, |
| 402 | GPIO2B1_MASK = 3 << GPIO2B1_SHIFT, |
| 403 | GPIO2B1_GPIO = 0, |
| 404 | GPIO2B1_GMAC_TXCLK, |
| 405 | |
| 406 | |
| 407 | GPIO2B0_SHIFT = 0, |
| 408 | GPIO2B0_MASK = 3 << GPIO2B0_SHIFT, |
| 409 | GPIO2B0_GPIO = 0, |
| 410 | GPIO2B0_GMAC_RXDV, |
| 411 | GPIO2B0_MAC_SPEED_IOUT, |
| 412 | }; |
| 413 | |
| 414 | /* GRF_GPIO2C_IOMUX */ |
| 415 | enum { |
| 416 | GPIO2C7_SHIFT = 14, |
| 417 | GPIO2C7_MASK = 3 << GPIO2C7_SHIFT, |
| 418 | GPIO2C7_GPIO = 0, |
| 419 | GPIO2C7_GMAC_TXD3, |
| 420 | |
| 421 | GPIO2C6_SHIFT = 12, |
| 422 | GPIO2C6_MASK = 3 << GPIO2C6_SHIFT, |
| 423 | GPIO2C6_GPIO = 0, |
| 424 | GPIO2C6_GMAC_TXD2, |
| 425 | |
| 426 | GPIO2C5_SHIFT = 10, |
| 427 | GPIO2C5_MASK = 3 << GPIO2C5_SHIFT, |
| 428 | GPIO2C5_GPIO = 0, |
| 429 | GPIO2C5_I2C2_SCL, |
| 430 | GPIO2C5_GMAC_RXD2, |
| 431 | |
| 432 | GPIO2C4_SHIFT = 8, |
| 433 | GPIO2C4_MASK = 3 << GPIO2C4_SHIFT, |
| 434 | GPIO2C4_GPIO = 0, |
| 435 | GPIO2C4_I2C2_SDA, |
| 436 | GPIO2C4_GMAC_RXD3, |
| 437 | |
| 438 | GPIO2C3_SHIFT = 6, |
| 439 | GPIO2C3_MASK = 3 << GPIO2C3_SHIFT, |
| 440 | GPIO2C3_GPIO = 0, |
| 441 | GPIO2C3_GMAC_TXD0, |
| 442 | |
| 443 | GPIO2C2_SHIFT = 4, |
| 444 | GPIO2C2_MASK = 3 << GPIO2C2_SHIFT, |
| 445 | GPIO2C2_GPIO = 0, |
| 446 | GPIO2C2_GMAC_TXD1, |
| 447 | |
| 448 | GPIO2C1_SHIFT = 2, |
| 449 | GPIO2C1_MASK = 3 << GPIO2C1_SHIFT, |
| 450 | GPIO2C1_GPIO = 0, |
| 451 | GPIO2C1_GMAC_RXD0, |
| 452 | |
| 453 | GPIO2C0_SHIFT = 0, |
| 454 | GPIO2C0_MASK = 3 << GPIO2C0_SHIFT, |
| 455 | GPIO2C0_GPIO = 0, |
| 456 | GPIO2C0_GMAC_RXD1, |
| 457 | }; |
| 458 | |
| 459 | /* GRF_GPIO2D_IOMUX */ |
| 460 | enum { |
| 461 | GPIO2D1_SHIFT = 2, |
| 462 | GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, |
| 463 | GPIO2D1_GPIO = 0, |
| 464 | GPIO2D1_GMAC_MDC, |
| 465 | |
| 466 | GPIO2D0_SHIFT = 0, |
| 467 | GPIO2D0_MASK = 3, |
| 468 | GPIO2D0_GPIO = 0, |
| 469 | GPIO2D0_GMAC_COL, |
| 470 | }; |
| 471 | |
| 472 | /* GRF_GPIO3C_IOMUX */ |
| 473 | enum { |
| 474 | GPIO3C6_SHIFT = 12, |
| 475 | GPIO3C6_MASK = 3 << GPIO3C6_SHIFT, |
| 476 | GPIO3C6_GPIO = 0, |
| 477 | GPIO3C6_DRV_VBUS1, |
| 478 | |
| 479 | GPIO3C5_SHIFT = 10, |
| 480 | GPIO3C5_MASK = 3 << GPIO3C5_SHIFT, |
| 481 | GPIO3C5_GPIO = 0, |
| 482 | GPIO3C5_PWM10, |
| 483 | |
| 484 | GPIO3C1_SHIFT = 2, |
| 485 | GPIO3C1_MASK = 3 << GPIO3C1_SHIFT, |
| 486 | GPIO3C1_GPIO = 0, |
| 487 | GPIO3C1_DRV_VBUS, |
| 488 | }; |
| 489 | |
| 490 | /* GRF_GPIO3D_IOMUX */ |
| 491 | enum { |
| 492 | GPIO3D2_SHIFT = 4, |
| 493 | GPIO3D2_MASK = 3 << GPIO3D2_SHIFT, |
| 494 | GPIO3D2_GPIO = 0, |
| 495 | GPIO3D2_PWM3, |
| 496 | }; |
| 497 | |
| 498 | /* GRF_CON_IOMUX */ |
| 499 | enum { |
| 500 | CON_IOMUX_GMAC_SHIFT = 15, |
| 501 | CON_IOMUX_GMAC_MASK = 1 << CON_IOMUX_GMAC_SHIFT, |
| 502 | CON_IOMUX_UART1SEL_SHIFT = 11, |
| 503 | CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT, |
| 504 | CON_IOMUX_UART2SEL_SHIFT = 8, |
| 505 | CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT, |
| 506 | CON_IOMUX_UART2SEL_2 = 0, |
| 507 | CON_IOMUX_UART2SEL_21, |
| 508 | CON_IOMUX_EMMCSEL_SHIFT = 7, |
| 509 | CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT, |
| 510 | CON_IOMUX_PWM3SEL_SHIFT = 3, |
| 511 | CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT, |
| 512 | CON_IOMUX_PWM2SEL_SHIFT = 2, |
| 513 | CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT, |
| 514 | CON_IOMUX_PWM1SEL_SHIFT = 1, |
| 515 | CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT, |
| 516 | CON_IOMUX_PWM0SEL_SHIFT = 0, |
| 517 | CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT, |
| 518 | }; |
| 519 | #endif |