| Peng Fan | 0a25e8b | 2017-02-22 16:21:41 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Based on Linux i.MX iomux-v3.h file: |
| 3 | * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, |
| 4 | * <armlinux@phytec.de> |
| 5 | * |
| 6 | * Copyright (C) 2016 Freescale Semiconductor, Inc. |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0+ |
| 9 | */ |
| 10 | |
| 11 | #ifndef __MACH_IOMUX_H__ |
| 12 | #define __MACH_IOMUX_H__ |
| 13 | |
| 14 | /* |
| 15 | * build IOMUX_PAD structure |
| 16 | * |
| 17 | * This iomux scheme is based around pads, which are the physical balls |
| 18 | * on the processor. |
| 19 | * |
| 20 | * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls |
| 21 | * things like driving strength and pullup/pulldown. |
| 22 | * - Each pad can have but not necessarily does have an output routing register |
| 23 | * (IOMUXC_SW_MUX_CTL_PAD_x). |
| 24 | * - Each pad can have but not necessarily does have an input routing register |
| 25 | * (IOMUXC_x_SELECT_INPUT) |
| 26 | * |
| 27 | * The three register sets do not have a fixed offset to each other, |
| 28 | * hence we order this table by pad control registers (which all pads |
| 29 | * have) and put the optional i/o routing registers into additional |
| 30 | * fields. |
| 31 | * |
| 32 | * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode> |
| 33 | * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> |
| 34 | * |
| 35 | * IOMUX/PAD Bit field definitions |
| 36 | * |
| 37 | * MUX_CTRL_OFS: 0..15 (16) |
| 38 | * SEL_INPUT_OFS: 16..31 (16) |
| 39 | * MUX_MODE: 32..37 (6) |
| 40 | * SEL_INP: 38..41 (4) |
| 41 | * PAD_CTRL + NO_PAD_CTRL: 42..60 (19) |
| 42 | * reserved: 61-63 (3) |
| 43 | */ |
| 44 | |
| 45 | typedef u64 iomux_cfg_t; |
| 46 | |
| 47 | #define MUX_CTRL_OFS_SHIFT 0 |
| 48 | #define MUX_CTRL_OFS_MASK ((iomux_cfg_t)0xffff << MUX_CTRL_OFS_SHIFT) |
| 49 | #define MUX_SEL_INPUT_OFS_SHIFT 16 |
| 50 | #define MUX_SEL_INPUT_OFS_MASK ((iomux_cfg_t)0xffff << \ |
| 51 | MUX_SEL_INPUT_OFS_SHIFT) |
| 52 | |
| 53 | #define MUX_MODE_SHIFT 32 |
| 54 | #define MUX_MODE_MASK ((iomux_cfg_t)0x3f << MUX_MODE_SHIFT) |
| 55 | #define MUX_SEL_INPUT_SHIFT 38 |
| 56 | #define MUX_SEL_INPUT_MASK ((iomux_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) |
| 57 | #define MUX_PAD_CTRL_SHIFT 42 |
| 58 | #define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0x7ffff << MUX_PAD_CTRL_SHIFT) |
| 59 | |
| 60 | #define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) |
| 61 | |
| 62 | #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ |
| 63 | sel_input, pad_ctrl) \ |
| 64 | (((iomux_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ |
| 65 | ((iomux_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \ |
| 66 | ((iomux_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ |
| 67 | ((iomux_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \ |
| 68 | ((iomux_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT)) |
| 69 | |
| 70 | #define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \ |
| 71 | MUX_PAD_CTRL(pad)) |
| 72 | |
| 73 | |
| 74 | #define IOMUX_CONFIG_MPORTS 0x20 |
| 75 | #define MUX_MODE_MPORTS ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \ |
| 76 | MUX_MODE_SHIFT) |
| 77 | |
| 78 | /* Bit definition below needs to be fixed acccording to ulp rm */ |
| 79 | |
| 80 | #define NO_PAD_CTRL (1 << 18) |
| 81 | #define PAD_CTL_OBE_ENABLE (1 << 17) |
| 82 | #define PAD_CTL_IBE_ENABLE (1 << 16) |
| 83 | #define PAD_CTL_DSE (1 << 6) |
| 84 | #define PAD_CTL_ODE (1 << 5) |
| 85 | #define PAD_CTL_SRE_FAST (0 << 2) |
| 86 | #define PAD_CTL_SRE_SLOW (1 << 2) |
| 87 | #define PAD_CTL_PUE (1 << 1) |
| 88 | #define PAD_CTL_PUS_UP ((1 << 0) | PAD_CTL_PUE) |
| 89 | #define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE) |
| 90 | |
| 91 | |
| 92 | void mx7ulp_iomux_setup_pad(iomux_cfg_t pad); |
| 93 | void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, |
| 94 | unsigned count); |
| 95 | #endif /* __MACH_IOMUX_H__*/ |