blob: 6b459831e74e2d03d33da44f63052a0209c9432f [file] [log] [blame]
Peng Fanf9220172019-08-27 06:26:08 +00001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 */
5
Jagan Teki73d51182021-04-26 18:23:46 +05306#include "imx8mm-u-boot.dtsi"
7
Marek Vasut4512d502020-04-29 15:04:24 +02008/ {
9 wdt-reboot {
10 compatible = "wdt-reboot";
11 wdt = <&wdog1>;
12 u-boot,dm-spl;
13 };
Clement Faurea93b0d92021-03-25 17:30:33 +080014
15 firmware {
16 optee {
17 compatible = "linaro,optee-tz";
18 method = "smc";
19 };
20 };
Marek Vasut4512d502020-04-29 15:04:24 +020021};
22
Andrey Zhizhikincf51a552020-12-05 17:29:17 +000023&reg_usdhc2_vmmc {
24 u-boot,off-on-delay-us = <20000>;
25};
26
Peng Fanf9220172019-08-27 06:26:08 +000027&pinctrl_reg_usdhc2_vmmc {
28 u-boot,dm-spl;
29};
30
31&pinctrl_uart2 {
32 u-boot,dm-spl;
33};
34
35&pinctrl_usdhc2_gpio {
36 u-boot,dm-spl;
37};
38
39&pinctrl_usdhc2 {
40 u-boot,dm-spl;
41};
42
43&pinctrl_usdhc3 {
44 u-boot,dm-spl;
45};
46
47&gpio1 {
48 u-boot,dm-spl;
49};
50
51&gpio2 {
52 u-boot,dm-spl;
53};
54
55&gpio3 {
56 u-boot,dm-spl;
57};
58
59&gpio4 {
60 u-boot,dm-spl;
61};
62
63&gpio5 {
64 u-boot,dm-spl;
65};
66
67&uart2 {
68 u-boot,dm-spl;
69};
70
71&usdhc1 {
72 u-boot,dm-spl;
73};
74
75&usdhc2 {
76 u-boot,dm-spl;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +000077 sd-uhs-sdr104;
78 sd-uhs-ddr50;
Haibo Chen26154952021-03-22 18:55:38 +080079 fsl,signal-voltage-switch-extra-delay-ms = <8>;
Peng Fanf9220172019-08-27 06:26:08 +000080};
81
82&usdhc3 {
83 u-boot,dm-spl;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +000084 mmc-hs400-1_8v;
85 mmc-hs400-enhanced-strobe;
Peng Fanf9220172019-08-27 06:26:08 +000086};
Peng Fana9e04332019-10-16 10:24:42 +000087
88&i2c1 {
89 u-boot,dm-spl;
90};
91
Ye Li79e69702021-03-19 15:56:55 +080092&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} {
Peng Fana9e04332019-10-16 10:24:42 +000093 u-boot,dm-spl;
94};
95
Ye Li79e69702021-03-19 15:56:55 +080096&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} {
Peng Fana9e04332019-10-16 10:24:42 +000097 u-boot,dm-spl;
98};
99
100&pinctrl_i2c1 {
101 u-boot,dm-spl;
102};
103
104&pinctrl_pmic {
105 u-boot,dm-spl;
106};
Peng Fane5f2b222019-10-22 03:30:04 +0000107
108&fec1 {
109 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
110};
Marek Vasut4512d502020-04-29 15:04:24 +0200111
112&wdog1 {
113 u-boot,dm-spl;
114};