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Simon Glassb2c1cac2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay23aee612020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -04005#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05306#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +01007
Simon Glassb2c1cac2014-02-26 15:59:21 -07008/ {
9 model = "sandbox";
10 compatible = "sandbox";
11 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060012 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070013
Simon Glassfef72b72014-07-23 06:55:03 -060014 aliases {
15 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -060016 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -070017 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -060018 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060019 gpio1 = &gpio_a;
20 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010021 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070022 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060023 mmc0 = "/mmc0";
24 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070025 pci0 = &pci0;
26 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070027 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020028 remoteproc0 = &rproc_1;
29 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060030 rtc0 = &rtc_0;
31 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060032 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020033 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070034 testbus3 = "/some-bus";
35 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070036 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070037 testfdt3 = "/b-test";
38 testfdt5 = "/some-bus/c-test@5";
39 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070040 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020041 fdt-dummy0 = "/translation-test@8000/dev@0,0";
42 fdt-dummy1 = "/translation-test@8000/dev@1,100";
43 fdt-dummy2 = "/translation-test@8000/dev@2,200";
44 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Dario Binacchib574d682020-12-30 00:16:21 +010045 fdt-dummy4 = "/translation-test@8000/xlatebus@4,400/devs/dev@19";
Simon Glass31680482015-03-25 12:23:05 -060046 usb0 = &usb_0;
47 usb1 = &usb_1;
48 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020049 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020050 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060051 };
52
Simon Glassed96cde2018-12-10 10:37:33 -070053 audio: audio-codec {
54 compatible = "sandbox,audio-codec";
55 #sound-dai-cells = <1>;
56 };
57
Philippe Reynes1ee26482020-07-24 18:19:51 +020058 buttons {
59 compatible = "gpio-keys";
60
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020061 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +020062 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020063 label = "button1";
Philippe Reynes1ee26482020-07-24 18:19:51 +020064 };
65
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020066 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +020067 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020068 label = "button2";
Philippe Reynes1ee26482020-07-24 18:19:51 +020069 };
70 };
71
Simon Glassc953aaf2018-12-10 10:37:34 -070072 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -060073 reg = <0 0>;
74 compatible = "google,cros-ec-sandbox";
75
76 /*
77 * This describes the flash memory within the EC. Note
78 * that the STM32L flash erases to 0, not 0xff.
79 */
80 flash {
81 image-pos = <0x08000000>;
82 size = <0x20000>;
83 erase-value = <0>;
84
85 /* Information for sandbox */
86 ro {
87 image-pos = <0>;
88 size = <0xf000>;
89 };
90 wp-ro {
91 image-pos = <0xf000>;
92 size = <0x1000>;
93 };
94 rw {
95 image-pos = <0x10000>;
96 size = <0x10000>;
97 };
98 };
99 };
100
Yannick Fertré9712c822019-10-07 15:29:05 +0200101 dsi_host: dsi_host {
102 compatible = "sandbox,dsi-host";
103 };
104
Simon Glassb2c1cac2014-02-26 15:59:21 -0700105 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600106 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700107 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600108 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700109 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600110 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100111 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
112 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700113 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100114 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
115 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
116 <&gpio_b 7 GPIO_IN 3 2 1>,
117 <&gpio_b 8 GPIO_OUT 3 2 1>,
118 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100119 test3-gpios =
120 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
121 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
122 <&gpio_c 2 GPIO_OUT>,
123 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
124 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200125 <&gpio_c 5 GPIO_IN>,
126 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
127 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530128 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
129 test5-gpios = <&gpio_a 19>;
130
Simon Glass6df01f92018-12-10 10:37:37 -0700131 int-value = <1234>;
132 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200133 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200134 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600135 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700136 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600137 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200138 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530139
140 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
141 <&muxcontroller0 2>, <&muxcontroller0 3>,
142 <&muxcontroller1>;
143 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
144 mux-syscon = <&syscon3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700145 };
146
147 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600148 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700149 compatible = "not,compatible";
150 };
151
152 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600153 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700154 };
155
Simon Glass5620cf82018-10-01 12:22:40 -0600156 backlight: backlight {
157 compatible = "pwm-backlight";
158 enable-gpios = <&gpio_a 1>;
159 power-supply = <&ldo_1>;
160 pwms = <&pwm 0 1000>;
161 default-brightness-level = <5>;
162 brightness-levels = <0 16 32 64 128 170 202 234 255>;
163 };
164
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200165 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200166 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200167 bind-test-child1 {
168 compatible = "sandbox,phy";
169 #phy-cells = <1>;
170 };
171
172 bind-test-child2 {
173 compatible = "simple-bus";
174 };
175 };
176
Simon Glassb2c1cac2014-02-26 15:59:21 -0700177 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600178 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700179 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600180 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700181 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530182
183 mux-controls = <&muxcontroller0 0>;
184 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700185 };
186
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200187 phy_provider0: gen_phy@0 {
188 compatible = "sandbox,phy";
189 #phy-cells = <1>;
190 };
191
192 phy_provider1: gen_phy@1 {
193 compatible = "sandbox,phy";
194 #phy-cells = <0>;
195 broken;
196 };
197
developer71092972020-05-02 11:35:12 +0200198 phy_provider2: gen_phy@2 {
199 compatible = "sandbox,phy";
200 #phy-cells = <0>;
201 };
202
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200203 gen_phy_user: gen_phy_user {
204 compatible = "simple-bus";
205 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
206 phy-names = "phy1", "phy2", "phy3";
207 };
208
developer71092972020-05-02 11:35:12 +0200209 gen_phy_user1: gen_phy_user1 {
210 compatible = "simple-bus";
211 phys = <&phy_provider0 0>, <&phy_provider2>;
212 phy-names = "phy1", "phy2";
213 };
214
Simon Glassb2c1cac2014-02-26 15:59:21 -0700215 some-bus {
216 #address-cells = <1>;
217 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600218 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600219 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600220 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700221 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600222 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700223 compatible = "denx,u-boot-fdt-test";
224 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600225 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700226 ping-add = <5>;
227 };
Simon Glass40717422014-07-23 06:55:18 -0600228 c-test@0 {
229 compatible = "denx,u-boot-fdt-test";
230 reg = <0>;
231 ping-expect = <6>;
232 ping-add = <6>;
233 };
234 c-test@1 {
235 compatible = "denx,u-boot-fdt-test";
236 reg = <1>;
237 ping-expect = <7>;
238 ping-add = <7>;
239 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700240 };
241
242 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600243 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600244 ping-expect = <6>;
245 ping-add = <6>;
246 compatible = "google,another-fdt-test";
247 };
248
249 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600250 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600251 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700252 ping-add = <6>;
253 compatible = "google,another-fdt-test";
254 };
255
Simon Glass0ccb0972015-01-25 08:27:05 -0700256 f-test {
257 compatible = "denx,u-boot-fdt-test";
258 };
259
260 g-test {
261 compatible = "denx,u-boot-fdt-test";
262 };
263
Bin Mengd9d24782018-10-10 22:07:01 -0700264 h-test {
265 compatible = "denx,u-boot-fdt-test1";
266 };
267
developercf8bc132020-05-02 11:35:10 +0200268 i-test {
269 compatible = "mediatek,u-boot-fdt-test";
270 #address-cells = <1>;
271 #size-cells = <0>;
272
273 subnode@0 {
274 reg = <0>;
275 };
276
277 subnode@1 {
278 reg = <1>;
279 };
280
281 subnode@2 {
282 reg = <2>;
283 };
284 };
285
Simon Glass204675c2019-12-29 21:19:25 -0700286 devres-test {
287 compatible = "denx,u-boot-devres-test";
288 };
289
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530290 another-test {
291 reg = <0 2>;
292 compatible = "denx,u-boot-fdt-test";
293 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
294 test5-gpios = <&gpio_a 19>;
295 };
296
Simon Glass3c601b12020-07-07 13:12:06 -0600297 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600298 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600299 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600300 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600301 child {
302 compatible = "denx,u-boot-acpi-test";
303 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600304 };
305
Simon Glass3c601b12020-07-07 13:12:06 -0600306 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600307 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600308 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600309 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600310 };
311
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200312 clocks {
313 clk_fixed: clk-fixed {
314 compatible = "fixed-clock";
315 #clock-cells = <0>;
316 clock-frequency = <1234>;
317 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000318
319 clk_fixed_factor: clk-fixed-factor {
320 compatible = "fixed-factor-clock";
321 #clock-cells = <0>;
322 clock-div = <3>;
323 clock-mult = <2>;
324 clocks = <&clk_fixed>;
325 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200326
327 osc {
328 compatible = "fixed-clock";
329 #clock-cells = <0>;
330 clock-frequency = <20000000>;
331 };
Stephen Warrena9622432016-06-17 09:44:00 -0600332 };
333
334 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600335 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600336 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200337 assigned-clocks = <&clk_sandbox 3>;
338 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600339 };
340
341 clk-test {
342 compatible = "sandbox,clk-test";
343 clocks = <&clk_fixed>,
344 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200345 <&clk_sandbox 0>,
346 <&clk_sandbox 3>,
347 <&clk_sandbox 2>;
348 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600349 };
350
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200351 ccf: clk-ccf {
352 compatible = "sandbox,clk-ccf";
353 };
354
Simon Glass5b968632015-05-22 15:42:15 -0600355 eth@10002000 {
356 compatible = "sandbox,eth";
357 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500358 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600359 };
360
361 eth_5: eth@10003000 {
362 compatible = "sandbox,eth";
363 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500364 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600365 };
366
Bin Meng04a11cb2015-08-27 22:25:53 -0700367 eth_3: sbe5 {
368 compatible = "sandbox,eth";
369 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500370 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700371 };
372
Simon Glass5b968632015-05-22 15:42:15 -0600373 eth@10004000 {
374 compatible = "sandbox,eth";
375 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500376 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600377 };
378
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700379 firmware {
380 sandbox_firmware: sandbox-firmware {
381 compatible = "sandbox,firmware";
382 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200383
384 sandbox-scmi-agent@0 {
385 compatible = "sandbox,scmi-agent";
386 #address-cells = <1>;
387 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200388
389 clk_scmi0: protocol@14 {
390 reg = <0x14>;
391 #clock-cells = <1>;
392 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200393
394 reset_scmi0: protocol@16 {
395 reg = <0x16>;
396 #reset-cells = <1>;
397 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200398 };
399
400 sandbox-scmi-agent@1 {
401 compatible = "sandbox,scmi-agent";
402 #address-cells = <1>;
403 #size-cells = <0>;
404
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200405 clk_scmi1: protocol@14 {
406 reg = <0x14>;
407 #clock-cells = <1>;
408 };
409
Etienne Carriere02fd1262020-09-09 18:44:00 +0200410 protocol@10 {
411 reg = <0x10>;
412 };
413 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700414 };
415
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100416 pinctrl-gpio {
417 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700418
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100419 gpio_a: base-gpios {
420 compatible = "sandbox,gpio";
421 gpio-controller;
422 #gpio-cells = <1>;
423 gpio-bank-name = "a";
424 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200425 hog_input_active_low {
426 gpio-hog;
427 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200428 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200429 };
430 hog_input_active_high {
431 gpio-hog;
432 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200433 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200434 };
435 hog_output_low {
436 gpio-hog;
437 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200438 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200439 };
440 hog_output_high {
441 gpio-hog;
442 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200443 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200444 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100445 };
446
447 gpio_b: extra-gpios {
448 compatible = "sandbox,gpio";
449 gpio-controller;
450 #gpio-cells = <5>;
451 gpio-bank-name = "b";
452 sandbox,gpio-count = <10>;
453 };
Simon Glass25348a42014-10-13 23:42:11 -0600454
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100455 gpio_c: pinmux-gpios {
456 compatible = "sandbox,gpio";
457 gpio-controller;
458 #gpio-cells = <2>;
459 gpio-bank-name = "c";
460 sandbox,gpio-count = <10>;
461 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100462 };
463
Simon Glass7df766e2014-12-10 08:55:55 -0700464 i2c@0 {
465 #address-cells = <1>;
466 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600467 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700468 compatible = "sandbox,i2c";
469 clock-frequency = <100000>;
470 eeprom@2c {
471 reg = <0x2c>;
472 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700473 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200474 partitions {
475 compatible = "fixed-partitions";
476 #address-cells = <1>;
477 #size-cells = <1>;
478 bootcount_i2c: bootcount@10 {
479 reg = <10 2>;
480 };
481 };
Simon Glass7df766e2014-12-10 08:55:55 -0700482 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200483
Simon Glass336b2952015-05-22 15:42:17 -0600484 rtc_0: rtc@43 {
485 reg = <0x43>;
486 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700487 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600488 };
489
490 rtc_1: rtc@61 {
491 reg = <0x61>;
492 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700493 sandbox,emul = <&emul1>;
494 };
495
496 i2c_emul: emul {
497 reg = <0xff>;
498 compatible = "sandbox,i2c-emul-parent";
499 emul_eeprom: emul-eeprom {
500 compatible = "sandbox,i2c-eeprom";
501 sandbox,filename = "i2c.bin";
502 sandbox,size = <256>;
503 };
504 emul0: emul0 {
505 compatible = "sandbox,i2c-rtc";
506 };
507 emul1: emull {
Simon Glass336b2952015-05-22 15:42:17 -0600508 compatible = "sandbox,i2c-rtc";
509 };
510 };
511
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200512 sandbox_pmic: sandbox_pmic {
513 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700514 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200515 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200516
517 mc34708: pmic@41 {
518 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700519 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200520 };
Simon Glass7df766e2014-12-10 08:55:55 -0700521 };
522
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100523 bootcount@0 {
524 compatible = "u-boot,bootcount-rtc";
525 rtc = <&rtc_1>;
526 offset = <0x13>;
527 };
528
Michal Simek4f18f922020-05-28 11:48:55 +0200529 bootcount {
530 compatible = "u-boot,bootcount-i2c-eeprom";
531 i2c-eeprom = <&bootcount_i2c>;
532 };
533
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100534 adc@0 {
535 compatible = "sandbox,adc";
536 vdd-supply = <&buck2>;
537 vss-microvolts = <0>;
538 };
539
Simon Glass515dcff2020-02-06 09:55:00 -0700540 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700541 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700542 interrupt-controller;
543 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700544 };
545
Simon Glass90b6fef2016-01-18 19:52:26 -0700546 lcd {
547 u-boot,dm-pre-reloc;
548 compatible = "sandbox,lcd-sdl";
549 xres = <1366>;
550 yres = <768>;
551 };
552
Simon Glassd783eb32015-07-06 12:54:34 -0600553 leds {
554 compatible = "gpio-leds";
555
556 iracibble {
557 gpios = <&gpio_a 1 0>;
558 label = "sandbox:red";
559 };
560
561 martinet {
562 gpios = <&gpio_a 2 0>;
563 label = "sandbox:green";
564 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200565
566 default_on {
567 gpios = <&gpio_a 5 0>;
568 label = "sandbox:default_on";
569 default-state = "on";
570 };
571
572 default_off {
573 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400574 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200575 default-state = "off";
576 };
Simon Glassd783eb32015-07-06 12:54:34 -0600577 };
578
Stephen Warren62f2c902016-05-16 17:41:37 -0600579 mbox: mbox {
580 compatible = "sandbox,mbox";
581 #mbox-cells = <1>;
582 };
583
584 mbox-test {
585 compatible = "sandbox,mbox-test";
586 mboxes = <&mbox 100>, <&mbox 1>;
587 mbox-names = "other", "test";
588 };
589
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900590 cpus {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400591 timebase-frequency = <2000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900592 cpu-test1 {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400593 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900594 compatible = "sandbox,cpu_sandbox";
595 u-boot,dm-pre-reloc;
596 };
Mario Sixdea5df72018-08-06 10:23:44 +0200597
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900598 cpu-test2 {
599 compatible = "sandbox,cpu_sandbox";
600 u-boot,dm-pre-reloc;
601 };
Mario Sixdea5df72018-08-06 10:23:44 +0200602
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900603 cpu-test3 {
604 compatible = "sandbox,cpu_sandbox";
605 u-boot,dm-pre-reloc;
606 };
Mario Sixdea5df72018-08-06 10:23:44 +0200607 };
608
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500609 chipid: chipid {
610 compatible = "sandbox,soc";
611 };
612
Simon Glassc953aaf2018-12-10 10:37:34 -0700613 i2s: i2s {
614 compatible = "sandbox,i2s";
615 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700616 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700617 };
618
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200619 nop-test_0 {
620 compatible = "sandbox,nop_sandbox1";
621 nop-test_1 {
622 compatible = "sandbox,nop_sandbox2";
623 bind = "True";
624 };
625 nop-test_2 {
626 compatible = "sandbox,nop_sandbox2";
627 bind = "False";
628 };
629 };
630
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200631 misc-test {
632 compatible = "sandbox,misc_sandbox";
633 };
634
Simon Glasse4fef742017-04-23 20:02:07 -0600635 mmc2 {
636 compatible = "sandbox,mmc";
637 };
638
639 mmc1 {
640 compatible = "sandbox,mmc";
641 };
642
643 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600644 compatible = "sandbox,mmc";
645 };
646
Simon Glass53a68b32019-02-16 20:24:50 -0700647 pch {
648 compatible = "sandbox,pch";
649 };
650
Tom Rini4a3ca482020-02-11 12:41:23 -0500651 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700652 compatible = "sandbox,pci";
653 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500654 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700655 #address-cells = <3>;
656 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600657 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700658 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700659 pci@0,0 {
660 compatible = "pci-generic";
661 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600662 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700663 };
Alex Margineanf1274432019-06-07 11:24:24 +0300664 pci@1,0 {
665 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600666 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
667 reg = <0x02000814 0 0 0 0
668 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600669 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300670 };
Simon Glass937bb472019-12-06 21:41:57 -0700671 p2sb-pci@2,0 {
672 compatible = "sandbox,p2sb";
673 reg = <0x02001010 0 0 0 0>;
674 sandbox,emul = <&p2sb_emul>;
675
676 adder {
677 intel,p2sb-port-id = <3>;
678 compatible = "sandbox,adder";
679 };
680 };
Simon Glass8c501022019-12-06 21:41:54 -0700681 pci@1e,0 {
682 compatible = "sandbox,pmc";
683 reg = <0xf000 0 0 0 0>;
684 sandbox,emul = <&pmc_emul1e>;
685 acpi-base = <0x400>;
686 gpe0-dwx-mask = <0xf>;
687 gpe0-dwx-shift-base = <4>;
688 gpe0-dw = <6 7 9>;
689 gpe0-sts = <0x20>;
690 gpe0-en = <0x30>;
691 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700692 pci@1f,0 {
693 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600694 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
695 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600696 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700697 };
698 };
699
Simon Glassb98ba4c2019-09-25 08:56:10 -0600700 pci-emul0 {
701 compatible = "sandbox,pci-emul-parent";
702 swap_case_emul0_0: emul0@0,0 {
703 compatible = "sandbox,swap-case";
704 };
705 swap_case_emul0_1: emul0@1,0 {
706 compatible = "sandbox,swap-case";
707 use-ea;
708 };
709 swap_case_emul0_1f: emul0@1f,0 {
710 compatible = "sandbox,swap-case";
711 };
Simon Glass937bb472019-12-06 21:41:57 -0700712 p2sb_emul: emul@2,0 {
713 compatible = "sandbox,p2sb-emul";
714 };
Simon Glass8c501022019-12-06 21:41:54 -0700715 pmc_emul1e: emul@1e,0 {
716 compatible = "sandbox,pmc-emul";
717 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600718 };
719
Tom Rini4a3ca482020-02-11 12:41:23 -0500720 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700721 compatible = "sandbox,pci";
722 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500723 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700724 #address-cells = <3>;
725 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -0700726 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
727 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
728 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700729 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200730 0x0c 0x00 0x1234 0x5678
731 0x10 0x00 0x1234 0x5678>;
732 pci@10,0 {
733 reg = <0x8000 0 0 0 0>;
734 };
Bin Meng408e5902018-08-03 01:14:41 -0700735 };
736
Tom Rini4a3ca482020-02-11 12:41:23 -0500737 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700738 compatible = "sandbox,pci";
739 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500740 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700741 #address-cells = <3>;
742 #size-cells = <2>;
743 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
744 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
745 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
746 pci@1f,0 {
747 compatible = "pci-generic";
748 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600749 sandbox,emul = <&swap_case_emul2_1f>;
750 };
751 };
752
753 pci-emul2 {
754 compatible = "sandbox,pci-emul-parent";
755 swap_case_emul2_1f: emul2@1f,0 {
756 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700757 };
758 };
759
Ramon Friedc64f19b2019-04-27 11:15:23 +0300760 pci_ep: pci_ep {
761 compatible = "sandbox,pci_ep";
762 };
763
Simon Glass9c433fe2017-04-23 20:10:44 -0600764 probing {
765 compatible = "simple-bus";
766 test1 {
767 compatible = "denx,u-boot-probe-test";
768 };
769
770 test2 {
771 compatible = "denx,u-boot-probe-test";
772 };
773
774 test3 {
775 compatible = "denx,u-boot-probe-test";
776 };
777
778 test4 {
779 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100780 first-syscon = <&syscon0>;
781 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +0100782 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600783 };
784 };
785
Stephen Warren92c67fa2016-07-13 13:45:31 -0600786 pwrdom: power-domain {
787 compatible = "sandbox,power-domain";
788 #power-domain-cells = <1>;
789 };
790
791 power-domain-test {
792 compatible = "sandbox,power-domain-test";
793 power-domains = <&pwrdom 2>;
794 };
795
Simon Glass5620cf82018-10-01 12:22:40 -0600796 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600797 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600798 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600799 };
800
801 pwm2 {
802 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600803 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600804 };
805
Simon Glass3d355e62015-07-06 12:54:31 -0600806 ram {
807 compatible = "sandbox,ram";
808 };
809
Simon Glassd860f222015-07-06 12:54:29 -0600810 reset@0 {
811 compatible = "sandbox,warm-reset";
812 };
813
814 reset@1 {
815 compatible = "sandbox,reset";
816 };
817
Stephen Warren6488e642016-06-17 09:43:59 -0600818 resetc: reset-ctl {
819 compatible = "sandbox,reset-ctl";
820 #reset-cells = <1>;
821 };
822
823 reset-ctl-test {
824 compatible = "sandbox,reset-ctl-test";
825 resets = <&resetc 100>, <&resetc 2>;
826 reset-names = "other", "test";
827 };
828
Sughosh Ganu23e37512019-12-28 23:58:31 +0530829 rng {
830 compatible = "sandbox,sandbox-rng";
831 };
832
Nishanth Menonedf85812015-09-17 15:42:41 -0500833 rproc_1: rproc@1 {
834 compatible = "sandbox,test-processor";
835 remoteproc-name = "remoteproc-test-dev1";
836 };
837
838 rproc_2: rproc@2 {
839 compatible = "sandbox,test-processor";
840 internal-memory-mapped;
841 remoteproc-name = "remoteproc-test-dev2";
842 };
843
Simon Glass5620cf82018-10-01 12:22:40 -0600844 panel {
845 compatible = "simple-panel";
846 backlight = <&backlight 0 100>;
847 };
848
Ramon Fried26ed32e2018-07-02 02:57:59 +0300849 smem@0 {
850 compatible = "sandbox,smem";
851 };
852
Simon Glass76072ac2018-12-10 10:37:36 -0700853 sound {
854 compatible = "sandbox,sound";
855 cpu {
856 sound-dai = <&i2s 0>;
857 };
858
859 codec {
860 sound-dai = <&audio 0>;
861 };
862 };
863
Simon Glass25348a42014-10-13 23:42:11 -0600864 spi@0 {
865 #address-cells = <1>;
866 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600867 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600868 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +0200869 cs-gpios = <0>, <0>, <&gpio_a 0>;
Simon Glass25348a42014-10-13 23:42:11 -0600870 spi.bin@0 {
871 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000872 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -0600873 spi-max-frequency = <40000000>;
874 sandbox,filename = "spi.bin";
875 };
Ovidiu Panaitae734732020-12-14 19:06:47 +0200876 spi.bin@1 {
877 reg = <1>;
878 compatible = "spansion,m25p16", "jedec,spi-nor";
879 spi-max-frequency = <50000000>;
880 sandbox,filename = "spi.bin";
881 spi-cpol;
882 spi-cpha;
883 };
Simon Glass25348a42014-10-13 23:42:11 -0600884 };
885
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100886 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -0600887 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +0200888 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -0600889 };
890
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100891 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -0600892 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600893 reg = <0x20 5
894 0x28 6
895 0x30 7
896 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600897 };
898
Patrick Delaunayee010432019-03-07 09:57:13 +0100899 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900900 compatible = "simple-mfd", "syscon";
901 reg = <0x40 5
902 0x48 6
903 0x50 7
904 0x58 8>;
905 };
906
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530907 syscon3: syscon@3 {
908 compatible = "simple-mfd", "syscon";
909 reg = <0x000100 0x10>;
910
911 muxcontroller0: a-mux-controller {
912 compatible = "mmio-mux";
913 #mux-control-cells = <1>;
914
915 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
916 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
917 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
918 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
919 u-boot,mux-autoprobe;
920 };
921 };
922
923 muxcontroller1: emul-mux-controller {
924 compatible = "mux-emul";
925 #mux-control-cells = <0>;
926 u-boot,mux-autoprobe;
927 idle-state = <0xabcd>;
928 };
929
Simon Glass791a17f2020-12-16 21:20:27 -0700930 testfdtm0 {
931 compatible = "denx,u-boot-fdtm-test";
932 };
933
934 testfdtm1: testfdtm1 {
935 compatible = "denx,u-boot-fdtm-test";
936 };
937
938 testfdtm2 {
939 compatible = "denx,u-boot-fdtm-test";
940 };
941
Sean Anderson79d3bba2020-09-28 10:52:23 -0400942 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800943 compatible = "sandbox,timer";
944 clock-frequency = <1000000>;
945 };
946
Sean Anderson79d3bba2020-09-28 10:52:23 -0400947 timer@1 {
948 compatible = "sandbox,timer";
949 sandbox,timebase-frequency-fallback;
950 };
951
Miquel Raynal80938c12018-05-15 11:57:27 +0200952 tpm2 {
953 compatible = "sandbox,tpm2";
954 };
955
Simon Glass5b968632015-05-22 15:42:15 -0600956 uart0: serial {
957 compatible = "sandbox,serial";
958 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500959 };
960
Simon Glass31680482015-03-25 12:23:05 -0600961 usb_0: usb@0 {
962 compatible = "sandbox,usb";
963 status = "disabled";
964 hub {
965 compatible = "sandbox,usb-hub";
966 #address-cells = <1>;
967 #size-cells = <0>;
968 flash-stick {
969 reg = <0>;
970 compatible = "sandbox,usb-flash";
971 };
972 };
973 };
974
975 usb_1: usb@1 {
976 compatible = "sandbox,usb";
977 hub {
978 compatible = "usb-hub";
979 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +0200980 #address-cells = <1>;
981 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -0600982 hub-emul {
983 compatible = "sandbox,usb-hub";
984 #address-cells = <1>;
985 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700986 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600987 reg = <0>;
988 compatible = "sandbox,usb-flash";
989 sandbox,filepath = "testflash.bin";
990 };
991
Simon Glass4700fe52015-11-08 23:48:01 -0700992 flash-stick@1 {
993 reg = <1>;
994 compatible = "sandbox,usb-flash";
995 sandbox,filepath = "testflash1.bin";
996 };
997
998 flash-stick@2 {
999 reg = <2>;
1000 compatible = "sandbox,usb-flash";
1001 sandbox,filepath = "testflash2.bin";
1002 };
1003
Simon Glassc0ccc722015-11-08 23:48:08 -07001004 keyb@3 {
1005 reg = <3>;
1006 compatible = "sandbox,usb-keyb";
1007 };
1008
Simon Glass31680482015-03-25 12:23:05 -06001009 };
Michael Walle7c961322020-06-02 01:47:07 +02001010
1011 usbstor@1 {
1012 reg = <1>;
1013 };
1014 usbstor@3 {
1015 reg = <3>;
1016 };
Simon Glass31680482015-03-25 12:23:05 -06001017 };
1018 };
1019
1020 usb_2: usb@2 {
1021 compatible = "sandbox,usb";
1022 status = "disabled";
1023 };
1024
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001025 spmi: spmi@0 {
1026 compatible = "sandbox,spmi";
1027 #address-cells = <0x1>;
1028 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001029 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001030 pm8916@0 {
1031 compatible = "qcom,spmi-pmic";
1032 reg = <0x0 0x1>;
1033 #address-cells = <0x1>;
1034 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001035 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001036
1037 spmi_gpios: gpios@c000 {
1038 compatible = "qcom,pm8916-gpio";
1039 reg = <0xc000 0x400>;
1040 gpio-controller;
1041 gpio-count = <4>;
1042 #gpio-cells = <2>;
1043 gpio-bank-name="spmi";
1044 };
1045 };
1046 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001047
1048 wdt0: wdt@0 {
1049 compatible = "sandbox,wdt";
1050 };
Rob Clarka471b672018-01-10 11:33:30 +01001051
Mario Six95922152018-08-09 14:51:19 +02001052 axi: axi@0 {
1053 compatible = "sandbox,axi";
1054 #address-cells = <0x1>;
1055 #size-cells = <0x1>;
1056 store@0 {
1057 compatible = "sandbox,sandbox_store";
1058 reg = <0x0 0x400>;
1059 };
1060 };
1061
Rob Clarka471b672018-01-10 11:33:30 +01001062 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001063 #address-cells = <1>;
1064 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001065 setting = "sunrise ohoka";
1066 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001067 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001068 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001069 chosen-test {
1070 compatible = "denx,u-boot-fdt-test";
1071 reg = <9 1>;
1072 };
1073 };
Mario Six35616ef2018-03-12 14:53:33 +01001074
1075 translation-test@8000 {
1076 compatible = "simple-bus";
1077 reg = <0x8000 0x4000>;
1078
1079 #address-cells = <0x2>;
1080 #size-cells = <0x1>;
1081
1082 ranges = <0 0x0 0x8000 0x1000
1083 1 0x100 0x9000 0x1000
1084 2 0x200 0xA000 0x1000
1085 3 0x300 0xB000 0x1000
Dario Binacchib574d682020-12-30 00:16:21 +01001086 4 0x400 0xC000 0x1000
Mario Six35616ef2018-03-12 14:53:33 +01001087 >;
1088
Fabien Dessenne22236e02019-05-31 15:11:30 +02001089 dma-ranges = <0 0x000 0x10000000 0x1000
1090 1 0x100 0x20000000 0x1000
1091 >;
1092
Mario Six35616ef2018-03-12 14:53:33 +01001093 dev@0,0 {
1094 compatible = "denx,u-boot-fdt-dummy";
1095 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001096 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001097 };
1098
1099 dev@1,100 {
1100 compatible = "denx,u-boot-fdt-dummy";
1101 reg = <1 0x100 0x1000>;
1102
1103 };
1104
1105 dev@2,200 {
1106 compatible = "denx,u-boot-fdt-dummy";
1107 reg = <2 0x200 0x1000>;
1108 };
1109
1110
1111 noxlatebus@3,300 {
1112 compatible = "simple-bus";
1113 reg = <3 0x300 0x1000>;
1114
1115 #address-cells = <0x1>;
1116 #size-cells = <0x0>;
1117
1118 dev@42 {
1119 compatible = "denx,u-boot-fdt-dummy";
1120 reg = <0x42>;
1121 };
1122 };
Dario Binacchib574d682020-12-30 00:16:21 +01001123
1124 xlatebus@4,400 {
1125 compatible = "sandbox,zero-size-cells-bus";
1126 reg = <4 0x400 0x1000>;
1127 #address-cells = <1>;
1128 #size-cells = <1>;
1129 ranges = <0 4 0x400 0x1000>;
1130
1131 devs {
1132 #address-cells = <1>;
1133 #size-cells = <0>;
1134
1135 dev@19 {
1136 compatible = "denx,u-boot-fdt-dummy";
1137 reg = <0x19>;
1138 };
1139 };
1140 };
1141
Mario Six35616ef2018-03-12 14:53:33 +01001142 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001143
1144 osd {
1145 compatible = "sandbox,sandbox_osd";
1146 };
Tom Rinib93eea72018-09-30 18:16:51 -04001147
Jens Wiklander86afaa62018-09-25 16:40:16 +02001148 sandbox_tee {
1149 compatible = "sandbox,tee";
1150 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001151
1152 sandbox_virtio1 {
1153 compatible = "sandbox,virtio1";
1154 };
1155
1156 sandbox_virtio2 {
1157 compatible = "sandbox,virtio2";
1158 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001159
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001160 sandbox_scmi {
1161 compatible = "sandbox,scmi-devices";
1162 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carriere8b9b6892020-09-09 18:44:07 +02001163 resets = <&reset_scmi0 3>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001164 };
1165
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001166 pinctrl {
1167 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001168
Sean Anderson3438e3b2020-09-14 11:01:57 -04001169 pinctrl-names = "default", "alternate";
1170 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1171 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001172
Sean Anderson3438e3b2020-09-14 11:01:57 -04001173 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001174 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001175 pins = "P5";
1176 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001177 bias-pull-up;
1178 input-disable;
1179 };
1180 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001181 pins = "P6";
1182 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001183 output-high;
1184 drive-open-drain;
1185 };
1186 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001187 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001188 bias-pull-down;
1189 input-enable;
1190 };
1191 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001192 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001193 bias-disable;
1194 };
1195 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001196
1197 pinctrl_i2c: i2c {
1198 groups {
1199 groups = "I2C_UART";
1200 function = "I2C";
1201 };
1202
1203 pins {
1204 pins = "P0", "P1";
1205 drive-open-drain;
1206 };
1207 };
1208
1209 pinctrl_i2s: i2s {
1210 groups = "SPI_I2S";
1211 function = "I2S";
1212 };
1213
1214 pinctrl_spi: spi {
1215 groups = "SPI_I2S";
1216 function = "SPI";
1217
1218 cs {
1219 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1220 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1221 };
1222 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001223 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001224
1225 hwspinlock@0 {
1226 compatible = "sandbox,hwspinlock";
1227 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001228
1229 dma: dma {
1230 compatible = "sandbox,dma";
1231 #dma-cells = <1>;
1232
1233 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1234 dma-names = "m2m", "tx0", "rx0";
1235 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001236
Alex Marginean0649be52019-07-12 10:13:53 +03001237 /*
1238 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1239 * end of the test. If parent mdio is removed first, clean-up of the
1240 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1241 * active at the end of the test. That it turn doesn't allow the mdio
1242 * class to be destroyed, triggering an error.
1243 */
1244 mdio-mux-test {
1245 compatible = "sandbox,mdio-mux";
1246 #address-cells = <1>;
1247 #size-cells = <0>;
1248 mdio-parent-bus = <&mdio>;
1249
1250 mdio-ch-test@0 {
1251 reg = <0>;
1252 };
1253 mdio-ch-test@1 {
1254 reg = <1>;
1255 };
1256 };
1257
1258 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001259 compatible = "sandbox,mdio";
1260 };
Sean Andersonb7860542020-06-24 06:41:12 -04001261
1262 pm-bus-test {
1263 compatible = "simple-pm-bus";
1264 clocks = <&clk_sandbox 4>;
1265 power-domains = <&pwrdom 1>;
1266 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001267
1268 resetc2: syscon-reset {
1269 compatible = "syscon-reset";
1270 #reset-cells = <1>;
1271 regmap = <&syscon0>;
1272 offset = <1>;
1273 mask = <0x27FFFFFF>;
1274 assert-high = <0>;
1275 };
1276
1277 syscon-reset-test {
1278 compatible = "sandbox,misc_sandbox";
1279 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1280 reset-names = "valid", "no_mask", "out_of_range";
1281 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301282
Simon Glass458b66a2020-11-05 06:32:05 -07001283 sysinfo {
1284 compatible = "sandbox,sysinfo-sandbox";
1285 };
1286
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301287 some_regmapped-bus {
1288 #address-cells = <0x1>;
1289 #size-cells = <0x1>;
1290
1291 ranges = <0x0 0x0 0x10>;
1292 compatible = "simple-bus";
1293
1294 regmap-test_0 {
1295 reg = <0 0x10>;
1296 compatible = "sandbox,regmap_test";
1297 };
1298 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001299};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001300
1301#include "sandbox_pmic.dtsi"