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git01.mediatek.com / filogic / uboot / 1a7665f71048db74868f7c335eafd9b6a5914492 / . / arch / powerpc / include / asm / fsl_portals.h
blob: 10d459e2bcfacc02adb9025adad95f251629c6cd [file] [log] [blame]
Kumar Gala38449a42009-09-10 03:02:13 -0500[diff] [blame]1/*
Haiying Wangd38d4b22011-03-01 09:30:07 -0500[diff] [blame]2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
Kumar Gala38449a42009-09-10 03:02:13 -0500[diff] [blame]3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala38449a42009-09-10 03:02:13 -0500[diff] [blame]5 */
6
7#ifndef _FSL_PORTALS_H_
8#define _FSL_PORTALS_H_
9
10/* entries must be in order and contiguous */
11enum fsl_dpaa_dev {
12 FSL_HW_PORTAL_SEC,
13#ifdef CONFIG_SYS_DPAA_FMAN
14 FSL_HW_PORTAL_FMAN1,
15#if (CONFIG_SYS_NUM_FMAN == 2)
16 FSL_HW_PORTAL_FMAN2,
17#endif
18#endif
Kumar Gala38449a42009-09-10 03:02:13 -0500[diff] [blame]19 FSL_HW_PORTAL_PME,
Kumar Gala9d8e8132011-09-10 10:44:13 -0500[diff] [blame]20#ifdef CONFIG_SYS_FSL_RAID_ENGINE
21 FSL_HW_PORTAL_RAID_ENGINE,
22#endif
Kumar Gala4eb3c372011-10-14 13:28:52 -0500[diff] [blame]23#ifdef CONFIG_SYS_DPAA_RMAN
24 FSL_HW_PORTAL_RMAN,
25#endif
Andy Fleming81177ad2012-10-08 07:44:18 +0000[diff] [blame]26#ifdef CONFIG_SYS_DPAA_DCE
27 FSL_HW_PORTAL_DCE,
28#endif
Kumar Gala4eb3c372011-10-14 13:28:52 -0500[diff] [blame]29
Kumar Gala38449a42009-09-10 03:02:13 -0500[diff] [blame]30};
31
32struct qportal_info {
33 u16 dliodn; /* DQRR LIODN */
34 u16 fliodn; /* frame data LIODN */
35 u16 liodn_offset;
36 u8 sdest;
37};
38
39#define SET_QP_INFO(dqrr, fdata, off, dest) \
40 { .dliodn = dqrr, .fliodn = fdata, .liodn_offset = off, .sdest = dest }
41
42extern int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev,
43 u32 *liodns, int liodn_offset);
Kumar Gala38449a42009-09-10 03:02:13 -0500[diff] [blame]44extern struct qportal_info qp_info[];
45extern void fdt_portal(void *blob, const char *compat, const char *container,
46 u64 addr, u32 size);
47
48#endif