| Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License |
| 6 | * Version 2 as published by the Free Software Foundation. |
| 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <asm/fsl_law.h> |
| 11 | |
| 12 | #include "ddr.h" |
| 13 | |
| 14 | unsigned int fsl_ddr_get_mem_data_rate(void); |
| 15 | |
| 16 | /* |
| 17 | * Round mclk_ps to nearest 10 ps in memory controller code. |
| 18 | * |
| 19 | * If an imprecise data rate is too high due to rounding error |
| 20 | * propagation, compute a suitably rounded mclk_ps to compute |
| 21 | * a working memory controller configuration. |
| 22 | */ |
| 23 | unsigned int get_memory_clk_period_ps(void) |
| 24 | { |
| 25 | unsigned int mclk_ps; |
| 26 | |
| 27 | mclk_ps = 2000000000000ULL / fsl_ddr_get_mem_data_rate(); |
| 28 | /* round to nearest 10 ps */ |
| 29 | return 10 * ((mclk_ps + 5) / 10); |
| 30 | } |
| 31 | |
| 32 | /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ |
| 33 | unsigned int picos_to_mclk(unsigned int picos) |
| 34 | { |
| 35 | const unsigned long long ULL_2e12 = 2000000000000ULL; |
| 36 | const unsigned long long ULL_8Fs = 0xFFFFFFFFULL; |
| 37 | unsigned long long clks; |
| 38 | unsigned long long clks_temp; |
| 39 | |
| 40 | if (!picos) |
| 41 | return 0; |
| 42 | |
| 43 | clks = fsl_ddr_get_mem_data_rate() * (unsigned long long) picos; |
| 44 | clks_temp = clks; |
| 45 | clks = clks / ULL_2e12; |
| 46 | if (clks_temp % ULL_2e12) { |
| 47 | clks++; |
| 48 | } |
| 49 | |
| 50 | if (clks > ULL_8Fs) { |
| 51 | clks = ULL_8Fs; |
| 52 | } |
| 53 | |
| 54 | return (unsigned int) clks; |
| 55 | } |
| 56 | |
| 57 | unsigned int mclk_to_picos(unsigned int mclk) |
| 58 | { |
| 59 | return get_memory_clk_period_ps() * mclk; |
| 60 | } |
| 61 | |
| 62 | void |
| 63 | __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, |
| 64 | unsigned int memctl_interleaved, |
| 65 | unsigned int ctrl_num) |
| 66 | { |
| 67 | /* |
| 68 | * If no DIMMs on this controller, do not proceed any further. |
| 69 | */ |
| 70 | if (!memctl_common_params->ndimms_present) { |
| 71 | return; |
| 72 | } |
| 73 | |
| 74 | if (ctrl_num == 0) { |
| 75 | /* |
| 76 | * Set up LAW for DDR controller 1 space. |
| 77 | */ |
| 78 | unsigned int lawbar1_target_id = memctl_interleaved |
| 79 | ? LAW_TRGT_IF_DDR_INTRLV : LAW_TRGT_IF_DDR_1; |
| 80 | |
| 81 | if (set_ddr_laws(memctl_common_params->base_address, |
| 82 | memctl_common_params->total_mem, |
| 83 | lawbar1_target_id) < 0) { |
| 84 | printf("ERROR\n"); |
| 85 | return ; |
| 86 | } |
| 87 | } else if (ctrl_num == 1) { |
| 88 | if (set_ddr_laws(memctl_common_params->base_address, |
| 89 | memctl_common_params->total_mem, |
| 90 | LAW_TRGT_IF_DDR_2) < 0) { |
| 91 | printf("ERROR\n"); |
| 92 | return ; |
| 93 | } |
| 94 | } else { |
| 95 | printf("unexpected controller number %u in %s\n", |
| 96 | ctrl_num, __FUNCTION__); |
| 97 | } |
| 98 | } |
| 99 | |
| 100 | __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void |
| 101 | fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, |
| 102 | unsigned int memctl_interleaved, |
| 103 | unsigned int ctrl_num); |