| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| masakazu.mochizuki.wd@hitachi.com | 9d0e937 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 2 | /* |
| 3 | * arch/arm/include/asm/arch-rmobile/r8a7792.h |
| 4 | * |
| 5 | * Copyright (C) 2016 Renesas Electronics Corporation |
| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 6 | */ |
| masakazu.mochizuki.wd@hitachi.com | 9d0e937 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 7 | |
| 8 | #ifndef __ASM_ARCH_R8A7792_H |
| 9 | #define __ASM_ARCH_R8A7792_H |
| 10 | |
| 11 | #include "rcar-base.h" |
| 12 | |
| masakazu.mochizuki.wd@hitachi.com | 9d0e937 | 2016-04-12 17:11:41 +0900 | [diff] [blame] | 13 | /* Module stop control/status register bits */ |
| 14 | #define MSTP0_BITS 0x00400801 |
| 15 | #define MSTP1_BITS 0x9B6F987F |
| 16 | #define MSTP2_BITS 0x108CE100 |
| 17 | #define MSTP3_BITS 0x20004010 |
| 18 | #define MSTP4_BITS 0x80000184 |
| 19 | #define MSTP5_BITS 0x44C00004 |
| 20 | #define MSTP7_BITS 0x01BF0000 |
| 21 | #define MSTP8_BITS 0x1FE01FB0 |
| 22 | #define MSTP9_BITS 0xFE2BFFB2 |
| 23 | #define MSTP10_BITS 0x00001820 |
| 24 | #define MSTP11_BITS 0x00000008 |
| 25 | |
| 26 | /* SDHI */ |
| 27 | #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1 |
| 28 | |
| 29 | #endif /* __ASM_ARCH_R8A7792_H */ |