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git01.mediatek.com / filogic / uboot / 1a4ea73b936eb1027b9bd56532001f6e43186ef3 / . / arch / arm / mach-socfpga / mmu-arm64_s10.c
blob: 91c6d7c55f134be8c7dd35aeee635b2fbf45f376 [file] [log] [blame]
Ley Foon Tanca6afad2018-05-24 00:17:26 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
Jit Loon Lim977071e2024-03-12 22:01:03 +0800[diff] [blame]3 * Copyright (C) 2016-2024 Intel Corporation <www.intel.com>
Ley Foon Tanca6afad2018-05-24 00:17:26 +0800[diff] [blame]4 *
5 */
6
7#include <common.h>
8#include <asm/armv8/mmu.h>
Simon Glass3ba929a2020-10-30 21:38:53 -0600[diff] [blame]9#include <asm/global_data.h>
Ley Foon Tanca6afad2018-05-24 00:17:26 +0800[diff] [blame]10
11DECLARE_GLOBAL_DATA_PTR;
12
Jit Loon Lim977071e2024-03-12 22:01:03 +0800[diff] [blame]13#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
14static struct mm_region socfpga_agilex5_mem_map[] = {
15 {
16 /* OCRAM 512KB */
17 .virt = 0x00000000UL,
18 .phys = 0x00000000UL,
19 .size = 0x00080000UL,
20 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
21 PTE_BLOCK_NON_SHARE,
22 }, {
23 /* DEVICE */
24 .virt = 0x10808000UL,
25 .phys = 0x10808000UL,
26 .size = 0x0F7F8000UL,
27 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
28 PTE_BLOCK_NON_SHARE |
29 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
30 }, {
31 /* FPGA 1.5GB */
32 .virt = 0x20000000UL,
33 .phys = 0x20000000UL,
34 .size = 0x60000000UL,
35 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
36 PTE_BLOCK_NON_SHARE |
37 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
38 }, {
39 /* FPGA 15GB */
40 .virt = 0x440000000UL,
41 .phys = 0x440000000UL,
42 .size = 0x3C0000000UL,
43 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
44 PTE_BLOCK_NON_SHARE |
45 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
46 }, {
47 /* FPGA 240GB */
48 .virt = 0x4400000000UL,
49 .phys = 0x4400000000UL,
50 .size = 0x3C00000000UL,
51 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
52 PTE_BLOCK_NON_SHARE |
53 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
54 }, {
55 /* MEM 2GB */
56 .virt = 0x80000000UL,
57 .phys = 0x80000000UL,
58 .size = 0x80000000UL,
59 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
60 PTE_BLOCK_INNER_SHARE,
61 }, {
62 /* List terminator */
63 },
64};
65
66struct mm_region *mem_map = socfpga_agilex5_mem_map;
67
68#else
Ley Foon Tanca6afad2018-05-24 00:17:26 +0800[diff] [blame]69static struct mm_region socfpga_stratix10_mem_map[] = {
70 {
71 /* MEM 2GB*/
72 .virt = 0x0UL,
73 .phys = 0x0UL,
74 .size = 0x80000000UL,
75 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
76 PTE_BLOCK_INNER_SHARE,
77 }, {
78 /* FPGA 1.5GB */
79 .virt = 0x80000000UL,
80 .phys = 0x80000000UL,
81 .size = 0x60000000UL,
82 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
83 PTE_BLOCK_NON_SHARE |
84 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
85 }, {
86 /* DEVICE 142MB */
87 .virt = 0xF7000000UL,
88 .phys = 0xF7000000UL,
89 .size = 0x08E00000UL,
90 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
91 PTE_BLOCK_NON_SHARE |
92 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
93 }, {
94 /* OCRAM 1MB but available 256KB */
95 .virt = 0xFFE00000UL,
96 .phys = 0xFFE00000UL,
97 .size = 0x00100000UL,
98 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
99 PTE_BLOCK_INNER_SHARE,
100 }, {
101 /* DEVICE 32KB */
102 .virt = 0xFFFC0000UL,
103 .phys = 0xFFFC0000UL,
104 .size = 0x00008000UL,
105 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
106 PTE_BLOCK_NON_SHARE |
107 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
108 }, {
109 /* MEM 124GB */
110 .virt = 0x0100000000UL,
111 .phys = 0x0100000000UL,
112 .size = 0x1F00000000UL,
113 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
114 PTE_BLOCK_INNER_SHARE,
115 }, {
116 /* DEVICE 4GB */
117 .virt = 0x2000000000UL,
118 .phys = 0x2000000000UL,
119 .size = 0x0100000000UL,
120 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
121 PTE_BLOCK_NON_SHARE |
122 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
123 }, {
124 /* List terminator */
125 },
126};
127
128struct mm_region *mem_map = socfpga_stratix10_mem_map;
Jit Loon Lim977071e2024-03-12 22:01:03 +0800[diff] [blame]129#endif