Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG |
| 4 | * Patrick Bruenn <p.bruenn@beckhoff.com> |
| 5 | * |
| 6 | * Configuration settings for Beckhoff CX9020. |
| 7 | * |
| 8 | * Based on Freescale's Linux i.MX mx53loco.h file: |
| 9 | * Copyright (C) 2010-2011 Freescale Semiconductor. |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | #ifndef __CONFIG_H |
| 13 | #define __CONFIG_H |
| 14 | |
| 15 | #include <asm/arch/imx-regs.h> |
| 16 | |
| 17 | #define CONFIG_CMDLINE_TAG |
| 18 | #define CONFIG_SETUP_MEMORY_TAGS |
| 19 | #define CONFIG_INITRD_TAG |
| 20 | |
| 21 | #define CONFIG_SYS_FSL_CLK |
| 22 | |
| 23 | /* Size of malloc() pool */ |
Steffen Dirkwinkel | ab0ed60 | 2019-10-23 07:40:43 +0200 | [diff] [blame] | 24 | #define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 25 | |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 26 | #define CONFIG_REVISION_TAG |
| 27 | |
| 28 | #define CONFIG_MXC_UART_BASE UART2_BASE |
| 29 | |
| 30 | #define CONFIG_FPGA_COUNT 1 |
| 31 | |
| 32 | /* MMC Configs */ |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 33 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
| 34 | #define CONFIG_SYS_FSL_ESDHC_NUM 2 |
| 35 | |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 36 | /* bootz: zImage/initrd.img support */ |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 37 | |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 38 | |
| 39 | /* USB Configs */ |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 40 | #define CONFIG_MXC_USB_PORT 1 |
| 41 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
| 42 | #define CONFIG_MXC_USB_FLAGS 0 |
| 43 | |
| 44 | /* allow to overwrite serial and ethaddr */ |
| 45 | #define CONFIG_ENV_OVERWRITE |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 46 | |
| 47 | /* Command definition */ |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 48 | |
| 49 | #define CONFIG_LOADADDR 0x70010000 /* loadaddr env var */ |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 50 | |
Steffen Dirkwinkel | ab0ed60 | 2019-10-23 07:40:43 +0200 | [diff] [blame] | 51 | #define BOOT_TARGET_DEVICES(func) \ |
| 52 | func(MMC, mmc, 0) \ |
| 53 | func(MMC, mmc, 1) \ |
| 54 | func(USB, usb, 0) \ |
| 55 | func(PXE, pxe, na) |
| 56 | |
| 57 | #include <config_distro_bootcmd.h> |
| 58 | |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 59 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Steffen Dirkwinkel | ab0ed60 | 2019-10-23 07:40:43 +0200 | [diff] [blame] | 60 | "fdt_addr_r=0x75000000\0" \ |
Patrick Bruenn | 2ef943e | 2017-07-11 11:23:21 +0200 | [diff] [blame] | 61 | "pxefile_addr_r=0x73000000\0" \ |
Steffen Dirkwinkel | ab0ed60 | 2019-10-23 07:40:43 +0200 | [diff] [blame] | 62 | "scriptaddr=0x74000000\0" \ |
| 63 | "ramdisk_addr_r=0x80000000\0" \ |
| 64 | "kernel_addr_r=0x72000000\0" \ |
| 65 | "fdt_high=0xffffffff\0" \ |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 66 | "console=ttymxc1,115200\0" \ |
Steffen Dirkwinkel | a2cab66 | 2019-10-23 07:40:42 +0200 | [diff] [blame] | 67 | "stdin=serial\0" \ |
| 68 | "stdout=serial,vidconsole\0" \ |
| 69 | "stderr=serial,vidconsole\0" \ |
Steffen Dirkwinkel | ab0ed60 | 2019-10-23 07:40:43 +0200 | [diff] [blame] | 70 | "fdtfile=imx53-cx9020.dtb\0" \ |
| 71 | BOOTENV |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 72 | |
| 73 | #define CONFIG_ARP_TIMEOUT 200UL |
| 74 | |
| 75 | /* Miscellaneous configurable options */ |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 76 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
| 77 | |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 78 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
| 79 | |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 80 | /* Physical Memory Map */ |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 81 | #define PHYS_SDRAM_1 CSD0_BASE_ADDR |
| 82 | #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) |
| 83 | #define PHYS_SDRAM_2 CSD1_BASE_ADDR |
| 84 | #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) |
| 85 | #define PHYS_SDRAM_SIZE (gd->ram_size) |
| 86 | |
| 87 | #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) |
| 88 | #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) |
| 89 | #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) |
| 90 | |
| 91 | #define CONFIG_SYS_INIT_SP_OFFSET \ |
| 92 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 93 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| 94 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
| 95 | |
Masahiro Yamada | 8cea9b5 | 2017-02-11 22:43:54 +0900 | [diff] [blame] | 96 | /* environment organization */ |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 97 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 98 | |
| 99 | /* Framebuffer and LCD */ |
Steffen Dirkwinkel | 3173618 | 2019-04-17 13:57:17 +0200 | [diff] [blame] | 100 | #define CONFIG_IMX_VIDEO_SKIP |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 101 | |
| 102 | #endif /* __CONFIG_H */ |