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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Phil Sutterd76eba62015-12-25 14:41:25 +01002/*
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
Phil Sutterd76eba62015-12-25 14:41:25 +01004 */
5
6#ifndef _CONFIG_SYNOLOGY_DS414_H
7#define _CONFIG_SYNOLOGY_DS414_H
8
9/*
10 * High Level Configuration Options (easy to change)
11 */
Phil Sutterd76eba62015-12-25 14:41:25 +010012
13/*
14 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
15 * for DDR ECC byte filling in the SPL before loading the main
16 * U-Boot into it.
17 */
Phil Sutterd76eba62015-12-25 14:41:25 +010018#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
19
20/*
21 * Commands configuration
22 */
Phil Sutterd76eba62015-12-25 14:41:25 +010023
24/* I2C */
25#define CONFIG_SYS_I2C
26#define CONFIG_SYS_I2C_MVTWSI
27#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
28#define CONFIG_SYS_I2C_SLAVE 0x0
29#define CONFIG_SYS_I2C_SPEED 100000
30
Phil Sutterd76eba62015-12-25 14:41:25 +010031/* Environment in SPI NOR flash */
Phil Sutterd76eba62015-12-25 14:41:25 +010032
Phil Sutterd76eba62015-12-25 14:41:25 +010033#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII
34
Phil Sutterd76eba62015-12-25 14:41:25 +010035/* PCIe support */
36#ifndef CONFIG_SPL_BUILD
Phil Sutterd76eba62015-12-25 14:41:25 +010037#define CONFIG_PCI_SCAN_SHOW
38#endif
39
40/* USB/EHCI/XHCI configuration */
41
Phil Sutterd76eba62015-12-25 14:41:25 +010042#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
43
44/* FIXME: broken XHCI support
45 * Below defines should enable support for the two rear USB3 ports. Sadly, this
46 * does not work because:
47 * - xhci-pci seems to not support DM_USB, so with that enabled it is not
48 * found.
49 * - USB init fails, controller does not respond in time */
Phil Sutterd76eba62015-12-25 14:41:25 +010050
Masahiro Yamada58d00232016-06-04 07:35:03 +090051#if !defined(CONFIG_USB_XHCI_HCD)
Phil Sutterd76eba62015-12-25 14:41:25 +010052#define CONFIG_EHCI_IS_TDI
53#endif
54
55/* why is this only defined in mv-common.h if CONFIG_DM is undefined? */
Phil Sutterd76eba62015-12-25 14:41:25 +010056
57/*
58 * mv-common.h should be defined after CMD configs since it used them
59 * to enable certain macros
60 */
61#include "mv-common.h"
62
63/*
64 * Memory layout while starting into the bin_hdr via the
65 * BootROM:
66 *
67 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
68 * 0x4000.4030 bin_hdr start address
69 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
70 * 0x4007.fffc BootROM stack top
71 *
72 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
73 * L2 cache thus cannot be used.
74 */
75
76/* SPL */
77/* Defines for SPL */
Phil Sutterd76eba62015-12-25 14:41:25 +010078#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
79
80#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
81#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
82
83#ifdef CONFIG_SPL_BUILD
84#define CONFIG_SYS_MALLOC_SIMPLE
85#endif
86
87#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
88#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
89
Ezra Buehler07e17ed2020-05-09 22:05:39 +020090#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI)
Phil Sutterd76eba62015-12-25 14:41:25 +010091/* SPL related SPI defines */
Ezra Buehler07e17ed2020-05-09 22:05:39 +020092#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
93#endif
Phil Sutterd76eba62015-12-25 14:41:25 +010094
95/* DS414 bus width is 32bits */
96#define CONFIG_DDR_32BIT
97
Phil Sutterd76eba62015-12-25 14:41:25 +010098/* Default Environment */
99#define CONFIG_BOOTCOMMAND "sf read ${loadaddr} 0xd0000 0x700000; bootm"
Phil Sutterd76eba62015-12-25 14:41:25 +0100100#define CONFIG_LOADADDR 0x80000
Phil Sutterd76eba62015-12-25 14:41:25 +0100101
102#endif /* _CONFIG_SYNOLOGY_DS414_H */