Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Bo Shen | c0eede0 | 2012-06-27 21:58:20 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2012 |
| 4 | * Atmel Semiconductor <www.atmel.com> |
| 5 | * Written-by: Bo Shen <voice.shen@atmel.com> |
Bo Shen | c0eede0 | 2012-06-27 21:58:20 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
Wenyou Yang | 11e2665 | 2016-08-05 08:57:35 +0800 | [diff] [blame] | 9 | #include <clk.h> |
| 10 | #include <dm.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 11 | #include <log.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 12 | #include <malloc.h> |
Bo Shen | c0eede0 | 2012-06-27 21:58:20 +0000 | [diff] [blame] | 13 | #include <usb.h> |
| 14 | #include <asm/io.h> |
Bo Shen | c0eede0 | 2012-06-27 21:58:20 +0000 | [diff] [blame] | 15 | #include <asm/arch/clk.h> |
| 16 | |
| 17 | #include "ehci.h" |
Bo Shen | c0eede0 | 2012-06-27 21:58:20 +0000 | [diff] [blame] | 18 | |
Sven Schwermer | 8a3cb9f1 | 2018-11-21 08:43:56 +0100 | [diff] [blame] | 19 | #if !CONFIG_IS_ENABLED(DM_USB) |
Wenyou Yang | 11e2665 | 2016-08-05 08:57:35 +0800 | [diff] [blame] | 20 | |
Troy Kisky | 7d6bbb9 | 2013-10-10 15:27:57 -0700 | [diff] [blame] | 21 | int ehci_hcd_init(int index, enum usb_init_type init, |
| 22 | struct ehci_hccr **hccr, struct ehci_hcor **hcor) |
Bo Shen | c0eede0 | 2012-06-27 21:58:20 +0000 | [diff] [blame] | 23 | { |
Bo Shen | c0eede0 | 2012-06-27 21:58:20 +0000 | [diff] [blame] | 24 | /* Enable UTMI PLL */ |
Wenyou Yang | 2f7be64 | 2016-02-02 11:11:53 +0800 | [diff] [blame] | 25 | if (at91_upll_clk_enable()) |
| 26 | return -1; |
Bo Shen | c0eede0 | 2012-06-27 21:58:20 +0000 | [diff] [blame] | 27 | |
| 28 | /* Enable USB Host clock */ |
Bo Shen | a2a637d | 2014-08-06 17:24:57 +0800 | [diff] [blame] | 29 | at91_periph_clk_enable(ATMEL_ID_UHPHS); |
Bo Shen | c0eede0 | 2012-06-27 21:58:20 +0000 | [diff] [blame] | 30 | |
Lucas Stach | 3494a4c | 2012-09-26 00:14:35 +0200 | [diff] [blame] | 31 | *hccr = (struct ehci_hccr *)ATMEL_BASE_EHCI; |
| 32 | *hcor = (struct ehci_hcor *)((uint32_t)*hccr + |
| 33 | HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); |
Bo Shen | c0eede0 | 2012-06-27 21:58:20 +0000 | [diff] [blame] | 34 | |
| 35 | return 0; |
| 36 | } |
| 37 | |
Lucas Stach | 3494a4c | 2012-09-26 00:14:35 +0200 | [diff] [blame] | 38 | int ehci_hcd_stop(int index) |
Bo Shen | c0eede0 | 2012-06-27 21:58:20 +0000 | [diff] [blame] | 39 | { |
Bo Shen | c0eede0 | 2012-06-27 21:58:20 +0000 | [diff] [blame] | 40 | /* Disable USB Host Clock */ |
Bo Shen | a2a637d | 2014-08-06 17:24:57 +0800 | [diff] [blame] | 41 | at91_periph_clk_disable(ATMEL_ID_UHPHS); |
Bo Shen | c0eede0 | 2012-06-27 21:58:20 +0000 | [diff] [blame] | 42 | |
Bo Shen | c0eede0 | 2012-06-27 21:58:20 +0000 | [diff] [blame] | 43 | /* Disable UTMI PLL */ |
Wenyou Yang | 2f7be64 | 2016-02-02 11:11:53 +0800 | [diff] [blame] | 44 | if (at91_upll_clk_disable()) |
| 45 | return -1; |
Bo Shen | c0eede0 | 2012-06-27 21:58:20 +0000 | [diff] [blame] | 46 | |
| 47 | return 0; |
| 48 | } |
Wenyou Yang | 11e2665 | 2016-08-05 08:57:35 +0800 | [diff] [blame] | 49 | |
| 50 | #else |
| 51 | |
| 52 | struct ehci_atmel_priv { |
| 53 | struct ehci_ctrl ehci; |
| 54 | }; |
| 55 | |
| 56 | static int ehci_atmel_enable_clk(struct udevice *dev) |
| 57 | { |
Wenyou Yang | 11e2665 | 2016-08-05 08:57:35 +0800 | [diff] [blame] | 58 | struct clk clk; |
Wenyou Yang | 11e2665 | 2016-08-05 08:57:35 +0800 | [diff] [blame] | 59 | int ret; |
| 60 | |
| 61 | ret = clk_get_by_index(dev, 0, &clk); |
| 62 | if (ret) |
| 63 | return ret; |
| 64 | |
| 65 | ret = clk_enable(&clk); |
| 66 | if (ret) |
| 67 | return ret; |
| 68 | |
| 69 | ret = clk_get_by_index(dev, 1, &clk); |
| 70 | if (ret) |
| 71 | return -EINVAL; |
| 72 | |
Wenyou Yang | 11e2665 | 2016-08-05 08:57:35 +0800 | [diff] [blame] | 73 | ret = clk_enable(&clk); |
| 74 | if (ret) |
| 75 | return ret; |
| 76 | |
| 77 | clk_free(&clk); |
| 78 | |
| 79 | return 0; |
| 80 | } |
| 81 | |
| 82 | static int ehci_atmel_probe(struct udevice *dev) |
| 83 | { |
| 84 | struct ehci_hccr *hccr; |
| 85 | struct ehci_hcor *hcor; |
| 86 | fdt_addr_t hcd_base; |
| 87 | int ret; |
| 88 | |
| 89 | ret = ehci_atmel_enable_clk(dev); |
| 90 | if (ret) { |
| 91 | debug("Failed to enable USB Host clock\n"); |
| 92 | return ret; |
| 93 | } |
| 94 | |
| 95 | /* |
| 96 | * Get the base address for EHCI controller from the device node |
| 97 | */ |
Simon Glass | ba1dea4 | 2017-05-17 17:18:05 -0600 | [diff] [blame] | 98 | hcd_base = devfdt_get_addr(dev); |
Wenyou Yang | 11e2665 | 2016-08-05 08:57:35 +0800 | [diff] [blame] | 99 | if (hcd_base == FDT_ADDR_T_NONE) { |
| 100 | debug("Can't get the EHCI register base address\n"); |
| 101 | return -ENXIO; |
| 102 | } |
| 103 | |
| 104 | hccr = (struct ehci_hccr *)hcd_base; |
| 105 | hcor = (struct ehci_hcor *) |
| 106 | ((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); |
| 107 | |
| 108 | debug("echi-atmel: init hccr %x and hcor %x hc_length %d\n", |
| 109 | (u32)hccr, (u32)hcor, |
| 110 | (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); |
| 111 | |
| 112 | return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST); |
| 113 | } |
| 114 | |
Wenyou Yang | 11e2665 | 2016-08-05 08:57:35 +0800 | [diff] [blame] | 115 | static const struct udevice_id ehci_usb_ids[] = { |
| 116 | { .compatible = "atmel,at91sam9g45-ehci", }, |
| 117 | { } |
| 118 | }; |
| 119 | |
| 120 | U_BOOT_DRIVER(ehci_atmel) = { |
| 121 | .name = "ehci_atmel", |
| 122 | .id = UCLASS_USB, |
| 123 | .of_match = ehci_usb_ids, |
| 124 | .probe = ehci_atmel_probe, |
Masahiro Yamada | d41919b | 2016-09-06 22:17:34 +0900 | [diff] [blame] | 125 | .remove = ehci_deregister, |
Wenyou Yang | 11e2665 | 2016-08-05 08:57:35 +0800 | [diff] [blame] | 126 | .ops = &ehci_usb_ops, |
| 127 | .platdata_auto_alloc_size = sizeof(struct usb_platdata), |
| 128 | .priv_auto_alloc_size = sizeof(struct ehci_atmel_priv), |
| 129 | .flags = DM_FLAG_ALLOC_PRIV_DMA, |
| 130 | }; |
| 131 | |
| 132 | #endif |