blob: c7f62b8b3ed0bdad57dc53e85288ed445faa67a9 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Ted Chen9b6dbd42016-01-20 14:24:52 +08002/*
3 * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
4 *
Ted Chen9b6dbd42016-01-20 14:24:52 +08005 */
6
7#ifndef _RTL8152_ETH_H
8#define _RTL8152_ETH_H
9
Simon Glass4dcacfc2020-05-10 11:40:13 -060010#include <linux/bitops.h>
Ted Chen9b6dbd42016-01-20 14:24:52 +080011#define R8152_BASE_NAME "r8152"
12
13#define PLA_IDR 0xc000
14#define PLA_RCR 0xc010
15#define PLA_RMS 0xc016
16#define PLA_RXFIFO_CTRL0 0xc0a0
17#define PLA_RXFIFO_CTRL1 0xc0a4
18#define PLA_RXFIFO_CTRL2 0xc0a8
19#define PLA_DMY_REG0 0xc0b0
20#define PLA_FMC 0xc0b4
21#define PLA_CFG_WOL 0xc0b6
22#define PLA_TEREDO_CFG 0xc0bc
23#define PLA_MAR 0xcd00
24#define PLA_BACKUP 0xd000
Hayes Wang1bb3ee42020-05-22 16:54:11 +080025#define PLA_BDC_CR 0xd1a0
Ted Chen9b6dbd42016-01-20 14:24:52 +080026#define PLA_TEREDO_TIMER 0xd2cc
27#define PLA_REALWOW_TIMER 0xd2e8
28#define PLA_LEDSEL 0xdd90
29#define PLA_LED_FEATURE 0xdd92
30#define PLA_PHYAR 0xde00
31#define PLA_BOOT_CTRL 0xe004
32#define PLA_GPHY_INTR_IMR 0xe022
33#define PLA_EEE_CR 0xe040
34#define PLA_EEEP_CR 0xe080
35#define PLA_MAC_PWR_CTRL 0xe0c0
36#define PLA_MAC_PWR_CTRL2 0xe0ca
37#define PLA_MAC_PWR_CTRL3 0xe0cc
38#define PLA_MAC_PWR_CTRL4 0xe0ce
39#define PLA_WDT6_CTRL 0xe428
40#define PLA_TCR0 0xe610
41#define PLA_TCR1 0xe612
42#define PLA_MTPS 0xe615
43#define PLA_TXFIFO_CTRL 0xe618
44#define PLA_RSTTALLY 0xe800
45#define BIST_CTRL 0xe810
46#define PLA_CR 0xe813
47#define PLA_CRWECR 0xe81c
48#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
49#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
50#define PLA_CONFIG5 0xe822
51#define PLA_PHY_PWR 0xe84c
52#define PLA_OOB_CTRL 0xe84f
53#define PLA_CPCR 0xe854
54#define PLA_MISC_0 0xe858
55#define PLA_MISC_1 0xe85a
56#define PLA_OCP_GPHY_BASE 0xe86c
57#define PLA_TALLYCNT 0xe890
58#define PLA_SFF_STS_7 0xe8de
59#define PLA_PHYSTATUS 0xe908
60#define PLA_BP_BA 0xfc26
61#define PLA_BP_0 0xfc28
62#define PLA_BP_1 0xfc2a
63#define PLA_BP_2 0xfc2c
64#define PLA_BP_3 0xfc2e
65#define PLA_BP_4 0xfc30
66#define PLA_BP_5 0xfc32
67#define PLA_BP_6 0xfc34
68#define PLA_BP_7 0xfc36
69#define PLA_BP_EN 0xfc38
70
71#define USB_USB2PHY 0xb41e
72#define USB_SSPHYLINK2 0xb428
73#define USB_U2P3_CTRL 0xb460
74#define USB_CSR_DUMMY1 0xb464
75#define USB_CSR_DUMMY2 0xb466
76#define USB_DEV_STAT 0xb808
77#define USB_CONNECT_TIMER 0xcbf8
78#define USB_BURST_SIZE 0xcfc0
79#define USB_USB_CTRL 0xd406
80#define USB_PHY_CTRL 0xd408
81#define USB_TX_AGG 0xd40a
82#define USB_RX_BUF_TH 0xd40c
83#define USB_USB_TIMER 0xd428
84#define USB_RX_EARLY_TIMEOUT 0xd42c
85#define USB_RX_EARLY_SIZE 0xd42e
86#define USB_PM_CTRL_STATUS 0xd432
87#define USB_TX_DMA 0xd434
88#define USB_TOLERANCE 0xd490
89#define USB_LPM_CTRL 0xd41a
90#define USB_UPS_CTRL 0xd800
91#define USB_MISC_0 0xd81a
92#define USB_POWER_CUT 0xd80a
93#define USB_AFE_CTRL2 0xd824
94#define USB_WDT11_CTRL 0xe43c
95#define USB_BP_BA 0xfc26
96#define USB_BP_0 0xfc28
97#define USB_BP_1 0xfc2a
98#define USB_BP_2 0xfc2c
99#define USB_BP_3 0xfc2e
100#define USB_BP_4 0xfc30
101#define USB_BP_5 0xfc32
102#define USB_BP_6 0xfc34
103#define USB_BP_7 0xfc36
104#define USB_BP_EN 0xfc38
105
106/* OCP Registers */
107#define OCP_ALDPS_CONFIG 0x2010
108#define OCP_EEE_CONFIG1 0x2080
109#define OCP_EEE_CONFIG2 0x2092
110#define OCP_EEE_CONFIG3 0x2094
111#define OCP_BASE_MII 0xa400
112#define OCP_EEE_AR 0xa41a
113#define OCP_EEE_DATA 0xa41c
114#define OCP_PHY_STATUS 0xa420
115#define OCP_POWER_CFG 0xa430
116#define OCP_EEE_CFG 0xa432
117#define OCP_SRAM_ADDR 0xa436
118#define OCP_SRAM_DATA 0xa438
119#define OCP_DOWN_SPEED 0xa442
120#define OCP_EEE_ABLE 0xa5c4
121#define OCP_EEE_ADV 0xa5d0
122#define OCP_EEE_LPABLE 0xa5d2
123#define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
124#define OCP_ADC_CFG 0xbc06
125
126/* SRAM Register */
127#define SRAM_LPF_CFG 0x8012
128#define SRAM_10M_AMP1 0x8080
129#define SRAM_10M_AMP2 0x8082
130#define SRAM_IMPEDANCE 0x8084
131
132/* PLA_RCR */
133#define RCR_AAP 0x00000001
134#define RCR_APM 0x00000002
135#define RCR_AM 0x00000004
136#define RCR_AB 0x00000008
137#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
138
139/* PLA_RXFIFO_CTRL0 */
140#define RXFIFO_THR1_NORMAL 0x00080002
141#define RXFIFO_THR1_OOB 0x01800003
142
143/* PLA_RXFIFO_CTRL1 */
144#define RXFIFO_THR2_FULL 0x00000060
145#define RXFIFO_THR2_HIGH 0x00000038
146#define RXFIFO_THR2_OOB 0x0000004a
147#define RXFIFO_THR2_NORMAL 0x00a0
148
149/* PLA_RXFIFO_CTRL2 */
150#define RXFIFO_THR3_FULL 0x00000078
151#define RXFIFO_THR3_HIGH 0x00000048
152#define RXFIFO_THR3_OOB 0x0000005a
153#define RXFIFO_THR3_NORMAL 0x0110
154
155/* PLA_TXFIFO_CTRL */
156#define TXFIFO_THR_NORMAL 0x00400008
157#define TXFIFO_THR_NORMAL2 0x01000008
158
159/* PLA_DMY_REG0 */
160#define ECM_ALDPS 0x0002
161
162/* PLA_FMC */
163#define FMC_FCR_MCU_EN 0x0001
164
165/* PLA_EEEP_CR */
166#define EEEP_CR_EEEP_TX 0x0002
167
168/* PLA_WDT6_CTRL */
169#define WDT6_SET_MODE 0x0010
170
171/* PLA_TCR0 */
172#define TCR0_TX_EMPTY 0x0800
173#define TCR0_AUTO_FIFO 0x0080
174
175/* PLA_TCR1 */
176#define VERSION_MASK 0x7cf0
177
178/* PLA_MTPS */
179#define MTPS_JUMBO (12 * 1024 / 64)
180#define MTPS_DEFAULT (6 * 1024 / 64)
181
182/* PLA_RSTTALLY */
183#define TALLY_RESET 0x0001
184
185/* PLA_CR */
186#define PLA_CR_RST 0x10
187#define PLA_CR_RE 0x08
188#define PLA_CR_TE 0x04
189
190/* PLA_BIST_CTRL */
191#define BIST_CTRL_SW_RESET (0x10 << 24)
192
193/* PLA_CRWECR */
194#define CRWECR_NORAML 0x00
195#define CRWECR_CONFIG 0xc0
196
197/* PLA_OOB_CTRL */
198#define NOW_IS_OOB 0x80
199#define TXFIFO_EMPTY 0x20
200#define RXFIFO_EMPTY 0x10
201#define LINK_LIST_READY 0x02
202#define DIS_MCU_CLROOB 0x01
203#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
204
205/* PLA_PHY_PWR */
206#define PLA_PHY_PWR_LLR (LINK_LIST_READY << 24)
207#define PLA_PHY_PWR_TXEMP (TXFIFO_EMPTY << 24)
208
209/* PLA_MISC_1 */
210#define RXDY_GATED_EN 0x0008
211
212/* PLA_SFF_STS_7 */
213#define RE_INIT_LL 0x8000
214#define MCU_BORW_EN 0x4000
215
216/* PLA_CPCR */
217#define CPCR_RX_VLAN 0x0040
218
219/* PLA_CFG_WOL */
220#define MAGIC_EN 0x0001
221
222/* PLA_TEREDO_CFG */
223#define TEREDO_SEL 0x8000
224#define TEREDO_WAKE_MASK 0x7f00
225#define TEREDO_RS_EVENT_MASK 0x00fe
226#define OOB_TEREDO_EN 0x0001
227
Hayes Wang1bb3ee42020-05-22 16:54:11 +0800228/* PLA_BDC_CR */
Ted Chen9b6dbd42016-01-20 14:24:52 +0800229#define ALDPS_PROXY_MODE 0x0001
230
231/* PLA_CONFIG34 */
232#define LINK_ON_WAKE_EN 0x0010
233#define LINK_OFF_WAKE_EN 0x0008
234
235/* PLA_CONFIG5 */
236#define BWF_EN 0x0040
237#define MWF_EN 0x0020
238#define UWF_EN 0x0010
239#define LAN_WAKE_EN 0x0002
240
241/* PLA_LED_FEATURE */
242#define LED_MODE_MASK 0x0700
243
244/* PLA_PHY_PWR */
245#define TX_10M_IDLE_EN 0x0080
246#define PFM_PWM_SWITCH 0x0040
247
248/* PLA_MAC_PWR_CTRL */
249#define D3_CLK_GATED_EN 0x00004000
250#define MCU_CLK_RATIO 0x07010f07
251#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
252#define ALDPS_SPDWN_RATIO 0x0f87
253
254/* PLA_MAC_PWR_CTRL2 */
255#define EEE_SPDWN_RATIO 0x8007
256
257/* PLA_MAC_PWR_CTRL3 */
258#define PKT_AVAIL_SPDWN_EN 0x0100
259#define SUSPEND_SPDWN_EN 0x0004
260#define U1U2_SPDWN_EN 0x0002
261#define L1_SPDWN_EN 0x0001
262
263/* PLA_MAC_PWR_CTRL4 */
264#define PWRSAVE_SPDWN_EN 0x1000
265#define RXDV_SPDWN_EN 0x0800
266#define TX10MIDLE_EN 0x0100
267#define TP100_SPDWN_EN 0x0020
268#define TP500_SPDWN_EN 0x0010
269#define TP1000_SPDWN_EN 0x0008
270#define EEE_SPDWN_EN 0x0001
271
272/* PLA_GPHY_INTR_IMR */
273#define GPHY_STS_MSK 0x0001
274#define SPEED_DOWN_MSK 0x0002
275#define SPDWN_RXDV_MSK 0x0004
276#define SPDWN_LINKCHG_MSK 0x0008
277
278/* PLA_PHYAR */
279#define PHYAR_FLAG 0x80000000
280
281/* PLA_EEE_CR */
282#define EEE_RX_EN 0x0001
283#define EEE_TX_EN 0x0002
284
285/* PLA_BOOT_CTRL */
286#define AUTOLOAD_DONE 0x0002
287
288/* USB_USB2PHY */
289#define USB2PHY_SUSPEND 0x0001
290#define USB2PHY_L1 0x0002
291
292/* USB_SSPHYLINK2 */
293#define pwd_dn_scale_mask 0x3ffe
294#define pwd_dn_scale(x) ((x) << 1)
295
296/* USB_CSR_DUMMY1 */
297#define DYNAMIC_BURST 0x0001
298
299/* USB_CSR_DUMMY2 */
300#define EP4_FULL_FC 0x0001
301
302/* USB_DEV_STAT */
303#define STAT_SPEED_MASK 0x0006
304#define STAT_SPEED_HIGH 0x0000
305#define STAT_SPEED_FULL 0x0002
306
307/* USB_TX_AGG */
308#define TX_AGG_MAX_THRESHOLD 0x03
309
310/* USB_RX_BUF_TH */
311#define RX_THR_SUPPER 0x0c350180
312#define RX_THR_HIGH 0x7a120180
313#define RX_THR_SLOW 0xffff0180
314
315/* USB_TX_DMA */
316#define TEST_MODE_DISABLE 0x00000001
317#define TX_SIZE_ADJUST1 0x00000100
318
319/* USB_UPS_CTRL */
320#define POWER_CUT 0x0100
321
322/* USB_PM_CTRL_STATUS */
323#define RESUME_INDICATE 0x0001
324
325/* USB_USB_CTRL */
326#define RX_AGG_DISABLE 0x0010
327#define RX_ZERO_EN 0x0080
328
329/* USB_U2P3_CTRL */
330#define U2P3_ENABLE 0x0001
331
332/* USB_POWER_CUT */
333#define PWR_EN 0x0001
334#define PHASE2_EN 0x0008
335
336/* USB_MISC_0 */
337#define PCUT_STATUS 0x0001
338
339/* USB_RX_EARLY_TIMEOUT */
340#define COALESCE_SUPER 85000U
341#define COALESCE_HIGH 250000U
342#define COALESCE_SLOW 524280U
343
344/* USB_WDT11_CTRL */
345#define TIMER11_EN 0x0001
346
347/* USB_LPM_CTRL */
348/* bit 4 ~ 5: fifo empty boundary */
349#define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
350/* bit 2 ~ 3: LMP timer */
351#define LPM_TIMER_MASK 0x0c
352#define LPM_TIMER_500MS 0x04 /* 500 ms */
353#define LPM_TIMER_500US 0x0c /* 500 us */
354#define ROK_EXIT_LPM 0x02
355
356/* USB_AFE_CTRL2 */
357#define SEN_VAL_MASK 0xf800
358#define SEN_VAL_NORMAL 0xa000
359#define SEL_RXIDLE 0x0100
360
361/* OCP_ALDPS_CONFIG */
362#define ENPWRSAVE 0x8000
363#define ENPDNPS 0x0200
364#define LINKENA 0x0100
365#define DIS_SDSAVE 0x0010
366
367/* OCP_PHY_STATUS */
368#define PHY_STAT_MASK 0x0007
369#define PHY_STAT_LAN_ON 3
370#define PHY_STAT_PWRDN 5
371
372/* OCP_POWER_CFG */
373#define EEE_CLKDIV_EN 0x8000
374#define EN_ALDPS 0x0004
375#define EN_10M_PLLOFF 0x0001
376
377/* OCP_EEE_CONFIG1 */
378#define RG_TXLPI_MSK_HFDUP 0x8000
379#define RG_MATCLR_EN 0x4000
380#define EEE_10_CAP 0x2000
381#define EEE_NWAY_EN 0x1000
382#define TX_QUIET_EN 0x0200
383#define RX_QUIET_EN 0x0100
384#define sd_rise_time_mask 0x0070
385#define sd_rise_time(x) (min((x), 7) << 4) /* bit 4 ~ 6 */
386#define RG_RXLPI_MSK_HFDUP 0x0008
387#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
388
389/* OCP_EEE_CONFIG2 */
390#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
391#define RG_DACQUIET_EN 0x0400
392#define RG_LDVQUIET_EN 0x0200
393#define RG_CKRSEL 0x0020
394#define RG_EEEPRG_EN 0x0010
395
396/* OCP_EEE_CONFIG3 */
397#define fast_snr_mask 0xff80
398#define fast_snr(x) (min((x), 0x1ff) << 7) /* bit 7 ~ 15 */
399#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
400#define MSK_PH 0x0006 /* bit 0 ~ 3 */
401
402/* OCP_EEE_AR */
403/* bit[15:14] function */
404#define FUN_ADDR 0x0000
405#define FUN_DATA 0x4000
406/* bit[4:0] device addr */
407
408/* OCP_EEE_CFG */
409#define CTAP_SHORT_EN 0x0040
410#define EEE10_EN 0x0010
411
412/* OCP_DOWN_SPEED */
413#define EN_10M_BGOFF 0x0080
414
415/* OCP_PHY_STATE */
416#define TXDIS_STATE 0x01
417#define ABD_STATE 0x02
418
419/* OCP_ADC_CFG */
420#define CKADSEL_L 0x0100
421#define ADC_EN 0x0080
422#define EN_EMI_L 0x0040
423
424/* SRAM_LPF_CFG */
425#define LPF_AUTO_TUNE 0x8000
426
427/* SRAM_10M_AMP1 */
428#define GDAC_IB_UPALL 0x0008
429
430/* SRAM_10M_AMP2 */
431#define AMP_DN 0x0200
432
433/* SRAM_IMPEDANCE */
434#define RX_DRIVING_MASK 0x6000
435
436#define RTL8152_MAX_TX 4
437#define RTL8152_MAX_RX 10
438#define INTBUFSIZE 2
439#define CRC_SIZE 4
440#define TX_ALIGN 4
441#define RX_ALIGN 8
442
443#define INTR_LINK 0x0004
444
445#define RTL8152_REQT_READ 0xc0
446#define RTL8152_REQT_WRITE 0x40
447#define RTL8152_REQ_GET_REGS 0x05
448#define RTL8152_REQ_SET_REGS 0x05
449
450#define BYTE_EN_DWORD 0xff
451#define BYTE_EN_WORD 0x33
452#define BYTE_EN_BYTE 0x11
453#define BYTE_EN_SIX_BYTES 0x3f
454#define BYTE_EN_START_MASK 0x0f
455#define BYTE_EN_END_MASK 0xf0
456
457#define RTL8152_ETH_FRAME_LEN 1514
458#define RTL8152_AGG_BUF_SZ 2048
459
460#define RTL8152_RMS (RTL8152_ETH_FRAME_LEN + CRC_SIZE)
461#define RTL8153_RMS (RTL8152_ETH_FRAME_LEN + CRC_SIZE)
462#define RTL8152_TX_TIMEOUT (5 * HZ)
463
464#define MCU_TYPE_PLA 0x0100
465#define MCU_TYPE_USB 0x0000
466
467/* The forced speed, 10Mb, 100Mb, gigabit. */
468#define SPEED_10 10
469#define SPEED_100 100
470#define SPEED_1000 1000
471
472#define SPEED_UNKNOWN -1
473
474/* Duplex, half or full. */
475#define DUPLEX_HALF 0x00
476#define DUPLEX_FULL 0x01
477#define DUPLEX_UNKNOWN 0xff
478
479/* Enable or disable autonegotiation. */
480#define AUTONEG_DISABLE 0x00
481#define AUTONEG_ENABLE 0x01
482
483/* Generic MII registers. */
484#define MII_BMCR 0x00 /* Basic mode control register */
485#define MII_BMSR 0x01 /* Basic mode status register */
486#define MII_PHYSID1 0x02 /* PHYS ID 1 */
487#define MII_PHYSID2 0x03 /* PHYS ID 2 */
488#define MII_ADVERTISE 0x04 /* Advertisement control reg */
489#define MII_LPA 0x05 /* Link partner ability reg */
490#define MII_EXPANSION 0x06 /* Expansion register */
491#define MII_CTRL1000 0x09 /* 1000BASE-T control */
492#define MII_STAT1000 0x0a /* 1000BASE-T status */
493#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
494#define MII_MMD_DATA 0x0e /* MMD Access Data Register */
495#define MII_ESTATUS 0x0f /* Extended Status */
496#define MII_DCOUNTER 0x12 /* Disconnect counter */
497#define MII_FCSCOUNTER 0x13 /* False carrier counter */
498#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
499#define MII_RERRCOUNTER 0x15 /* Receive error counter */
500#define MII_SREVISION 0x16 /* Silicon revision */
501#define MII_RESV1 0x17 /* Reserved... */
502#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
503#define MII_PHYADDR 0x19 /* PHY address */
504#define MII_RESV2 0x1a /* Reserved... */
505#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
506#define MII_NCONFIG 0x1c /* Network interface config */
507
508#define TIMEOUT_RESOLUTION 50
509#define PHY_CONNECT_TIMEOUT 5000
510#define USB_BULK_SEND_TIMEOUT 5000
511#define USB_BULK_RECV_TIMEOUT 5000
512#define R8152_WAIT_TIMEOUT 2000
513
514struct rx_desc {
515 __le32 opts1;
516#define RD_CRC BIT(15)
517#define RX_LEN_MASK 0x7fff
518
519 __le32 opts2;
520#define RD_UDP_CS BIT(23)
521#define RD_TCP_CS BIT(22)
522#define RD_IPV6_CS BIT(20)
523#define RD_IPV4_CS BIT(19)
524
525 __le32 opts3;
526#define IPF BIT(23) /* IP checksum fail */
527#define UDPF BIT(22) /* UDP checksum fail */
528#define TCPF BIT(21) /* TCP checksum fail */
529#define RX_VLAN_TAG BIT(16)
530
531 __le32 opts4;
532 __le32 opts5;
533 __le32 opts6;
534};
535
536struct tx_desc {
537 __le32 opts1;
538#define TX_FS BIT(31) /* First segment of a packet */
539#define TX_LS BIT(30) /* Final segment of a packet */
540#define LGSEND BIT(29)
541#define GTSENDV4 BIT(28)
542#define GTSENDV6 BIT(27)
543#define GTTCPHO_SHIFT 18
544#define GTTCPHO_MAX 0x7fU
545#define TX_LEN_MAX 0x3ffffU
546
547 __le32 opts2;
548#define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
549#define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
550#define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
551#define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
552#define MSS_SHIFT 17
553#define MSS_MAX 0x7ffU
554#define TCPHO_SHIFT 17
555#define TCPHO_MAX 0x7ffU
556#define TX_VLAN_TAG BIT(16)
557};
558
559enum rtl_version {
560 RTL_VER_UNKNOWN = 0,
561 RTL_VER_01,
562 RTL_VER_02,
563 RTL_VER_03,
564 RTL_VER_04,
565 RTL_VER_05,
566 RTL_VER_06,
567 RTL_VER_07,
568 RTL_VER_MAX
569};
570
571enum rtl_register_content {
572 _1000bps = 0x10,
573 _100bps = 0x08,
574 _10bps = 0x04,
575 LINK_STATUS = 0x02,
576 FULL_DUP = 0x01,
577};
578
579struct r8152 {
580 struct usb_device *udev;
581 struct usb_interface *intf;
582 bool supports_gmii;
583
584 struct rtl_ops {
585 void (*init)(struct r8152 *);
586 int (*enable)(struct r8152 *);
587 void (*disable)(struct r8152 *);
588 void (*up)(struct r8152 *);
589 void (*down)(struct r8152 *);
590 void (*unload)(struct r8152 *);
591 } rtl_ops;
592
593 u32 coalesce;
594 u16 ocp_base;
595
596 u8 version;
Stefan Roese47c50972016-06-29 07:58:05 +0200597
598#ifdef CONFIG_DM_ETH
599 struct ueth_data ueth;
600#endif
Ted Chen9b6dbd42016-01-20 14:24:52 +0800601};
602
603int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
604 u16 size, void *data, u16 type);
605int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
606 void *data, u16 type);
607
608int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data);
609int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
610 u16 size, void *data);
611
612int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data);
613int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
614 u16 size, void *data);
615
616u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index);
617void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data);
618
619u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index);
620void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data);
621
622u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index);
623void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data);
624
625u16 ocp_reg_read(struct r8152 *tp, u16 addr);
626void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data);
627
628void sram_write(struct r8152 *tp, u16 addr, u16 data);
629
630int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index,
631 const u32 mask, bool set, unsigned int timeout);
632
633void r8152b_firmware(struct r8152 *tp);
634void r8153_firmware(struct r8152 *tp);
635#endif