Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Alexander Graf | fce8e5c | 2018-01-23 18:05:21 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2018 Alexander Graf <agraf@suse.de> |
| 4 | * |
| 5 | * Based on drivers/pinctrl/mvebu/pinctrl-mvebu.c and |
| 6 | * drivers/gpio/bcm2835_gpio.c |
| 7 | * |
| 8 | * This driver gets instantiated by the GPIO driver, because both devices |
| 9 | * share the same device node. |
Alexander Graf | fce8e5c | 2018-01-23 18:05:21 +0100 | [diff] [blame] | 10 | * https://spdx.org/licenses |
| 11 | */ |
| 12 | |
| 13 | #include <common.h> |
| 14 | #include <config.h> |
| 15 | #include <errno.h> |
| 16 | #include <dm.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 17 | #include <log.h> |
Alexander Graf | fce8e5c | 2018-01-23 18:05:21 +0100 | [diff] [blame] | 18 | #include <dm/pinctrl.h> |
| 19 | #include <dm/root.h> |
| 20 | #include <dm/device-internal.h> |
| 21 | #include <dm/lists.h> |
| 22 | #include <asm/system.h> |
| 23 | #include <asm/io.h> |
| 24 | #include <asm/gpio.h> |
| 25 | |
| 26 | struct bcm283x_pinctrl_priv { |
| 27 | u32 *base_reg; |
| 28 | }; |
| 29 | |
| 30 | #define MAX_PINS_PER_BANK 16 |
| 31 | |
| 32 | static void bcm2835_gpio_set_func_id(struct udevice *dev, unsigned int gpio, |
| 33 | int func) |
| 34 | { |
| 35 | struct bcm283x_pinctrl_priv *priv = dev_get_priv(dev); |
| 36 | int reg_offset; |
| 37 | int field_offset; |
| 38 | |
| 39 | reg_offset = BCM2835_GPIO_FSEL_BANK(gpio); |
| 40 | field_offset = BCM2835_GPIO_FSEL_SHIFT(gpio); |
| 41 | |
| 42 | clrsetbits_le32(&priv->base_reg[reg_offset], |
| 43 | BCM2835_GPIO_FSEL_MASK << field_offset, |
| 44 | (func & BCM2835_GPIO_FSEL_MASK) << field_offset); |
| 45 | } |
| 46 | |
| 47 | static int bcm2835_gpio_get_func_id(struct udevice *dev, unsigned int gpio) |
| 48 | { |
| 49 | struct bcm283x_pinctrl_priv *priv = dev_get_priv(dev); |
| 50 | u32 val; |
| 51 | |
| 52 | val = readl(&priv->base_reg[BCM2835_GPIO_FSEL_BANK(gpio)]); |
| 53 | |
| 54 | return (val >> BCM2835_GPIO_FSEL_SHIFT(gpio) & BCM2835_GPIO_FSEL_MASK); |
| 55 | } |
| 56 | |
| 57 | /* |
| 58 | * bcm283x_pinctrl_set_state: configure pin functions. |
| 59 | * @dev: the pinctrl device to be configured. |
| 60 | * @config: the state to be configured. |
| 61 | * @return: 0 in success |
| 62 | */ |
| 63 | int bcm283x_pinctrl_set_state(struct udevice *dev, struct udevice *config) |
| 64 | { |
| 65 | u32 pin_arr[MAX_PINS_PER_BANK]; |
| 66 | u32 function; |
| 67 | int i, len, pin_count = 0; |
| 68 | |
| 69 | if (!dev_read_prop(config, "brcm,pins", &len) || !len || |
| 70 | len & 0x3 || dev_read_u32_array(config, "brcm,pins", pin_arr, |
| 71 | len / sizeof(u32))) { |
| 72 | debug("Failed reading pins array for pinconfig %s (%d)\n", |
| 73 | config->name, len); |
| 74 | return -EINVAL; |
| 75 | } |
| 76 | |
| 77 | pin_count = len / sizeof(u32); |
| 78 | |
| 79 | function = dev_read_u32_default(config, "brcm,function", -1); |
| 80 | if (function < 0) { |
| 81 | debug("Failed reading function for pinconfig %s (%d)\n", |
| 82 | config->name, function); |
| 83 | return -EINVAL; |
| 84 | } |
| 85 | |
| 86 | for (i = 0; i < pin_count; i++) |
| 87 | bcm2835_gpio_set_func_id(dev, pin_arr[i], function); |
| 88 | |
| 89 | return 0; |
| 90 | } |
| 91 | |
| 92 | static int bcm283x_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, |
| 93 | int index) |
| 94 | { |
| 95 | if (banknum != 0) |
| 96 | return -EINVAL; |
| 97 | |
| 98 | return bcm2835_gpio_get_func_id(dev, index); |
| 99 | } |
| 100 | |
| 101 | static const struct udevice_id bcm2835_pinctrl_id[] = { |
| 102 | {.compatible = "brcm,bcm2835-gpio"}, |
Matthias Brugger | 8c9901f | 2019-11-06 15:28:25 +0100 | [diff] [blame] | 103 | {.compatible = "brcm,bcm2711-gpio"}, |
Alexander Graf | fce8e5c | 2018-01-23 18:05:21 +0100 | [diff] [blame] | 104 | {} |
| 105 | }; |
| 106 | |
| 107 | int bcm283x_pinctl_probe(struct udevice *dev) |
| 108 | { |
| 109 | struct bcm283x_pinctrl_priv *priv; |
| 110 | int ret; |
| 111 | struct udevice *pdev; |
| 112 | |
| 113 | priv = dev_get_priv(dev); |
| 114 | if (!priv) { |
| 115 | debug("%s: Failed to get private\n", __func__); |
| 116 | return -EINVAL; |
| 117 | } |
| 118 | |
| 119 | priv->base_reg = dev_read_addr_ptr(dev); |
| 120 | if (priv->base_reg == (void *)FDT_ADDR_T_NONE) { |
| 121 | debug("%s: Failed to get base address\n", __func__); |
| 122 | return -EINVAL; |
| 123 | } |
| 124 | |
| 125 | /* Create GPIO device as well */ |
| 126 | ret = device_bind(dev, lists_driver_lookup_name("gpio_bcm2835"), |
| 127 | "gpio_bcm2835", NULL, dev_of_offset(dev), &pdev); |
| 128 | if (ret) { |
| 129 | /* |
| 130 | * While we really want the pinctrl driver to work to make |
| 131 | * devices go where they should go, the GPIO controller is |
| 132 | * not quite as crucial as it's only rarely used, so don't |
| 133 | * fail here. |
| 134 | */ |
| 135 | printf("Failed to bind GPIO driver\n"); |
| 136 | } |
| 137 | |
| 138 | return 0; |
| 139 | } |
| 140 | |
| 141 | static struct pinctrl_ops bcm283x_pinctrl_ops = { |
| 142 | .set_state = bcm283x_pinctrl_set_state, |
| 143 | .get_gpio_mux = bcm283x_pinctrl_get_gpio_mux, |
| 144 | }; |
| 145 | |
| 146 | U_BOOT_DRIVER(pinctrl_bcm283x) = { |
| 147 | .name = "bcm283x_pinctrl", |
| 148 | .id = UCLASS_PINCTRL, |
| 149 | .of_match = of_match_ptr(bcm2835_pinctrl_id), |
| 150 | .priv_auto_alloc_size = sizeof(struct bcm283x_pinctrl_priv), |
| 151 | .ops = &bcm283x_pinctrl_ops, |
Alexander Graf | 7fcd313 | 2018-01-25 12:05:56 +0100 | [diff] [blame] | 152 | .probe = bcm283x_pinctl_probe, |
Matthias Brugger | 501b684 | 2019-11-08 14:49:48 +0100 | [diff] [blame] | 153 | #if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_BOARD) |
Alexander Graf | 7fcd313 | 2018-01-25 12:05:56 +0100 | [diff] [blame] | 154 | .flags = DM_FLAG_PRE_RELOC, |
Bin Meng | c2908c6 | 2018-10-24 06:36:33 -0700 | [diff] [blame] | 155 | #endif |
Alexander Graf | fce8e5c | 2018-01-23 18:05:21 +0100 | [diff] [blame] | 156 | }; |