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git01.mediatek.com / filogic / uboot / 1a3732cb2575df75dcf83479a7d69266eff9745a / . / drivers / clk / imx / clk-imx8mm.c
blob: 66c9601b0c13b72349906c6156a2d825ec3c77dd [file] [log] [blame]
Peng Fan525c8762019-08-19 07:54:04 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2019 NXP
4 * Peng Fan <peng.fan@nxp.com>
5 */
6
7#include <common.h>
8#include <clk.h>
9#include <clk-uclass.h>
10#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -0600[diff] [blame]11#include <log.h>
Peng Fan525c8762019-08-19 07:54:04 +0000[diff] [blame]12#include <asm/arch/clock.h>
13#include <asm/arch/imx-regs.h>
14#include <dt-bindings/clock/imx8mm-clock.h>
15
16#include "clk.h"
17
18#define PLL_1416X_RATE(_rate, _m, _p, _s) \
19 { \
20 .rate = (_rate), \
21 .mdiv = (_m), \
22 .pdiv = (_p), \
23 .sdiv = (_s), \
24 }
25
26#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
27 { \
28 .rate = (_rate), \
29 .mdiv = (_m), \
30 .pdiv = (_p), \
31 .sdiv = (_s), \
32 .kdiv = (_k), \
33 }
34
35static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
36 PLL_1416X_RATE(1800000000U, 225, 3, 0),
37 PLL_1416X_RATE(1600000000U, 200, 3, 0),
38 PLL_1416X_RATE(1200000000U, 300, 3, 1),
39 PLL_1416X_RATE(1000000000U, 250, 3, 1),
40 PLL_1416X_RATE(800000000U, 200, 3, 1),
41 PLL_1416X_RATE(750000000U, 250, 2, 2),
42 PLL_1416X_RATE(700000000U, 350, 3, 2),
43 PLL_1416X_RATE(600000000U, 300, 3, 2),
44};
45
46static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
47 PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
48};
49
50static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
51 .type = PLL_1443X,
52 .rate_table = imx8mm_drampll_tbl,
53 .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
54};
55
56static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
57 .type = PLL_1416X,
58 .rate_table = imx8mm_pll1416x_tbl,
59 .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
60};
61
62static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
63 .type = PLL_1416X,
64 .rate_table = imx8mm_pll1416x_tbl,
65 .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
66};
67
68static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
69static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
70static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
71static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
72static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
73static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
74
75static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
76 "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
77
Frieder Schrempf2d82cf82019-10-23 16:36:44 +0000[diff] [blame]78static const char *imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
Peng Fan525c8762019-08-19 07:54:04 +0000[diff] [blame]79 "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
80
81static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
82 "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
83
Peng Fanee5515d2019-10-22 03:29:48 +0000[diff] [blame]84#ifndef CONFIG_SPL_BUILD
85static const char *imx8mm_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
86 "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
87
88static const char *imx8mm_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
89 "clk_ext3", "clk_ext4", "video_pll1_out", };
90
91static const char *imx8mm_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
92 "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
93#endif
94
Peng Fan525c8762019-08-19 07:54:04 +0000[diff] [blame]95static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
96 "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
97
98static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
99 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
100
101static const char *imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
102 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
103
104static const char *imx8mm_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
105 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
106
107static const char *imx8mm_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
108 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
109
110static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
111 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
112
113static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
114 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
115
116static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
117 "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
118
119static const char *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
120 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
121
122static ulong imx8mm_clk_get_rate(struct clk *clk)
123{
124 struct clk *c;
125 int ret;
126
127 debug("%s(#%lu)\n", __func__, clk->id);
128
129 ret = clk_get_by_id(clk->id, &c);
130 if (ret)
131 return ret;
132
133 return clk_get_rate(c);
134}
135
136static ulong imx8mm_clk_set_rate(struct clk *clk, unsigned long rate)
137{
138 struct clk *c;
139 int ret;
140
141 debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
142
143 ret = clk_get_by_id(clk->id, &c);
144 if (ret)
145 return ret;
146
147 return clk_set_rate(c, rate);
148}
149
150static int __imx8mm_clk_enable(struct clk *clk, bool enable)
151{
152 struct clk *c;
153 int ret;
154
155 debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
156
157 ret = clk_get_by_id(clk->id, &c);
158 if (ret)
159 return ret;
160
161 if (enable)
162 ret = clk_enable(c);
163 else
164 ret = clk_disable(c);
165
166 return ret;
167}
168
169static int imx8mm_clk_disable(struct clk *clk)
170{
171 return __imx8mm_clk_enable(clk, 0);
172}
173
174static int imx8mm_clk_enable(struct clk *clk)
175{
176 return __imx8mm_clk_enable(clk, 1);
177}
178
Peng Fan7adf5872019-10-22 03:29:51 +0000[diff] [blame]179static int imx8mm_clk_set_parent(struct clk *clk, struct clk *parent)
180{
181 struct clk *c, *cp;
182 int ret;
183
184 debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
185
186 ret = clk_get_by_id(clk->id, &c);
187 if (ret)
188 return ret;
189
190 ret = clk_get_by_id(parent->id, &cp);
191 if (ret)
192 return ret;
193
194 return clk_set_parent(c, cp);
195}
196
Peng Fan525c8762019-08-19 07:54:04 +0000[diff] [blame]197static struct clk_ops imx8mm_clk_ops = {
198 .set_rate = imx8mm_clk_set_rate,
199 .get_rate = imx8mm_clk_get_rate,
200 .enable = imx8mm_clk_enable,
201 .disable = imx8mm_clk_disable,
Peng Fan7adf5872019-10-22 03:29:51 +0000[diff] [blame]202 .set_parent = imx8mm_clk_set_parent,
Peng Fan525c8762019-08-19 07:54:04 +0000[diff] [blame]203};
204
205static int imx8mm_clk_probe(struct udevice *dev)
206{
207 void __iomem *base;
208
209 base = (void *)ANATOP_BASE_ADDR;
210
211 clk_dm(IMX8MM_DRAM_PLL_REF_SEL,
212 imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
213 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
214 clk_dm(IMX8MM_ARM_PLL_REF_SEL,
215 imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
216 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
217 clk_dm(IMX8MM_SYS_PLL1_REF_SEL,
218 imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
219 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
220 clk_dm(IMX8MM_SYS_PLL2_REF_SEL,
221 imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
222 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
223 clk_dm(IMX8MM_SYS_PLL3_REF_SEL,
224 imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
225 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
226
227 clk_dm(IMX8MM_DRAM_PLL,
228 imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
229 base + 0x50, &imx8mm_dram_pll));
230 clk_dm(IMX8MM_ARM_PLL,
231 imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
232 base + 0x84, &imx8mm_arm_pll));
233 clk_dm(IMX8MM_SYS_PLL1,
234 imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
235 base + 0x94, &imx8mm_sys_pll));
236 clk_dm(IMX8MM_SYS_PLL2,
237 imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
238 base + 0x104, &imx8mm_sys_pll));
239 clk_dm(IMX8MM_SYS_PLL3,
240 imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
241 base + 0x114, &imx8mm_sys_pll));
242
243 /* PLL bypass out */
244 clk_dm(IMX8MM_DRAM_PLL_BYPASS,
245 imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
246 dram_pll_bypass_sels,
247 ARRAY_SIZE(dram_pll_bypass_sels),
248 CLK_SET_RATE_PARENT));
249 clk_dm(IMX8MM_ARM_PLL_BYPASS,
250 imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
251 arm_pll_bypass_sels,
252 ARRAY_SIZE(arm_pll_bypass_sels),
253 CLK_SET_RATE_PARENT));
254 clk_dm(IMX8MM_SYS_PLL1_BYPASS,
255 imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
256 sys_pll1_bypass_sels,
257 ARRAY_SIZE(sys_pll1_bypass_sels),
258 CLK_SET_RATE_PARENT));
259 clk_dm(IMX8MM_SYS_PLL2_BYPASS,
260 imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
261 sys_pll2_bypass_sels,
262 ARRAY_SIZE(sys_pll2_bypass_sels),
263 CLK_SET_RATE_PARENT));
264 clk_dm(IMX8MM_SYS_PLL3_BYPASS,
265 imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
266 sys_pll3_bypass_sels,
267 ARRAY_SIZE(sys_pll3_bypass_sels),
268 CLK_SET_RATE_PARENT));
269
270 /* PLL out gate */
271 clk_dm(IMX8MM_DRAM_PLL_OUT,
272 imx_clk_gate("dram_pll_out", "dram_pll_bypass",
273 base + 0x50, 13));
274 clk_dm(IMX8MM_ARM_PLL_OUT,
275 imx_clk_gate("arm_pll_out", "arm_pll_bypass",
276 base + 0x84, 11));
277 clk_dm(IMX8MM_SYS_PLL1_OUT,
278 imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
279 base + 0x94, 11));
280 clk_dm(IMX8MM_SYS_PLL2_OUT,
281 imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
282 base + 0x104, 11));
283 clk_dm(IMX8MM_SYS_PLL3_OUT,
284 imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
285 base + 0x114, 11));
286
287 /* SYS PLL fixed output */
288 clk_dm(IMX8MM_SYS_PLL1_40M,
289 imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
290 clk_dm(IMX8MM_SYS_PLL1_80M,
291 imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
292 clk_dm(IMX8MM_SYS_PLL1_100M,
293 imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
294 clk_dm(IMX8MM_SYS_PLL1_133M,
295 imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
296 clk_dm(IMX8MM_SYS_PLL1_160M,
297 imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
298 clk_dm(IMX8MM_SYS_PLL1_200M,
299 imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
300 clk_dm(IMX8MM_SYS_PLL1_266M,
301 imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
302 clk_dm(IMX8MM_SYS_PLL1_400M,
303 imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
304 clk_dm(IMX8MM_SYS_PLL1_800M,
305 imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
306
307 clk_dm(IMX8MM_SYS_PLL2_50M,
308 imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
309 clk_dm(IMX8MM_SYS_PLL2_100M,
310 imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
311 clk_dm(IMX8MM_SYS_PLL2_125M,
312 imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
313 clk_dm(IMX8MM_SYS_PLL2_166M,
314 imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
315 clk_dm(IMX8MM_SYS_PLL2_200M,
316 imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
317 clk_dm(IMX8MM_SYS_PLL2_250M,
318 imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
319 clk_dm(IMX8MM_SYS_PLL2_333M,
320 imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
321 clk_dm(IMX8MM_SYS_PLL2_500M,
322 imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
323 clk_dm(IMX8MM_SYS_PLL2_1000M,
324 imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
325
326 base = dev_read_addr_ptr(dev);
Sean Andersonb58106d2019-12-24 23:57:47 -0500[diff] [blame]327 if (!base)
Peng Fan525c8762019-08-19 07:54:04 +0000[diff] [blame]328 return -EINVAL;
329
330 clk_dm(IMX8MM_CLK_A53_SRC,
331 imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
332 imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels)));
333 clk_dm(IMX8MM_CLK_A53_CG,
334 imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
335 clk_dm(IMX8MM_CLK_A53_DIV,
336 imx_clk_divider2("arm_a53_div", "arm_a53_cg",
337 base + 0x8000, 0, 3));
338
339 clk_dm(IMX8MM_CLK_AHB,
340 imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels,
341 base + 0x9000));
342 clk_dm(IMX8MM_CLK_IPG_ROOT,
343 imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
344
345 clk_dm(IMX8MM_CLK_ENET_AXI,
346 imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels,
347 base + 0x8880));
348 clk_dm(IMX8MM_CLK_NAND_USDHC_BUS,
349 imx8m_clk_composite_critical("nand_usdhc_bus",
350 imx8mm_nand_usdhc_sels,
351 base + 0x8900));
352
353 /* IP */
354 clk_dm(IMX8MM_CLK_USDHC1,
355 imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels,
356 base + 0xac00));
357 clk_dm(IMX8MM_CLK_USDHC2,
358 imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels,
359 base + 0xac80));
360 clk_dm(IMX8MM_CLK_I2C1,
361 imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00));
362 clk_dm(IMX8MM_CLK_I2C2,
363 imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80));
364 clk_dm(IMX8MM_CLK_I2C3,
365 imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
366 clk_dm(IMX8MM_CLK_I2C4,
367 imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
368 clk_dm(IMX8MM_CLK_WDOG,
369 imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
370 clk_dm(IMX8MM_CLK_USDHC3,
371 imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels,
372 base + 0xbc80));
373
374 clk_dm(IMX8MM_CLK_I2C1_ROOT,
375 imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
376 clk_dm(IMX8MM_CLK_I2C2_ROOT,
377 imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
378 clk_dm(IMX8MM_CLK_I2C3_ROOT,
379 imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
380 clk_dm(IMX8MM_CLK_I2C4_ROOT,
381 imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
382 clk_dm(IMX8MM_CLK_OCOTP_ROOT,
383 imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
384 clk_dm(IMX8MM_CLK_USDHC1_ROOT,
385 imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
386 clk_dm(IMX8MM_CLK_USDHC2_ROOT,
387 imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
388 clk_dm(IMX8MM_CLK_WDOG1_ROOT,
389 imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
390 clk_dm(IMX8MM_CLK_WDOG2_ROOT,
391 imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
392 clk_dm(IMX8MM_CLK_WDOG3_ROOT,
393 imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
394 clk_dm(IMX8MM_CLK_USDHC3_ROOT,
395 imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
396
Peng Fanee5515d2019-10-22 03:29:48 +0000[diff] [blame]397 /* clks not needed in SPL stage */
398#ifndef CONFIG_SPL_BUILD
399 clk_dm(IMX8MM_CLK_ENET_REF,
400 imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels,
401 base + 0xa980));
402 clk_dm(IMX8MM_CLK_ENET_TIMER,
403 imx8m_clk_composite("enet_timer", imx8mm_enet_timer_sels,
404 base + 0xaa00));
405 clk_dm(IMX8MM_CLK_ENET_PHY_REF,
406 imx8m_clk_composite("enet_phy", imx8mm_enet_phy_sels,
407 base + 0xaa80));
408 clk_dm(IMX8MM_CLK_ENET1_ROOT,
409 imx_clk_gate4("enet1_root_clk", "enet_axi",
410 base + 0x40a0, 0));
411#endif
412
Peng Fan525c8762019-08-19 07:54:04 +0000[diff] [blame]413#ifdef CONFIG_SPL_BUILD
414 struct clk *clkp, *clkp1;
415
416 clk_get_by_id(IMX8MM_CLK_WDOG1_ROOT, &clkp);
417 clk_enable(clkp);
418 clk_get_by_id(IMX8MM_CLK_WDOG2_ROOT, &clkp);
419 clk_enable(clkp);
420 clk_get_by_id(IMX8MM_CLK_WDOG3_ROOT, &clkp);
421 clk_enable(clkp);
422
423 /* Configure SYS_PLL3 to 750MHz */
424 clk_get_by_id(IMX8MM_SYS_PLL3, &clkp);
425 clk_set_rate(clkp, 750000000UL);
426 clk_enable(clkp);
427
428 /* Configure ARM to sys_pll2_500m */
429 clk_get_by_id(IMX8MM_CLK_A53_SRC, &clkp);
430 clk_get_by_id(IMX8MM_SYS_PLL2_OUT, &clkp1);
431 clk_enable(clkp1);
432 clk_get_by_id(IMX8MM_SYS_PLL2_500M, &clkp1);
433 clk_set_parent(clkp, clkp1);
434
435 /* Configure ARM PLL to 1.2GHz */
436 clk_get_by_id(IMX8MM_ARM_PLL, &clkp1);
437 clk_set_rate(clkp1, 1200000000UL);
438 clk_get_by_id(IMX8MM_ARM_PLL_OUT, &clkp1);
439 clk_enable(clkp1);
440 clk_set_parent(clkp, clkp1);
441
442 /* Configure DIV to 1.2GHz */
443 clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp1);
444 clk_set_rate(clkp1, 1200000000UL);
445#endif
446
447 return 0;
448}
449
450static const struct udevice_id imx8mm_clk_ids[] = {
451 { .compatible = "fsl,imx8mm-ccm" },
452 { },
453};
454
455U_BOOT_DRIVER(imx8mm_clk) = {
456 .name = "clk_imx8mm",
457 .id = UCLASS_CLK,
458 .of_match = imx8mm_clk_ids,
459 .ops = &imx8mm_clk_ops,
460 .probe = imx8mm_clk_probe,
461 .flags = DM_FLAG_PRE_RELOC,
462};