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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Prabhakar Kushwaha768e1202013-09-12 11:11:28 +05302/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
Biwen Li29cd2712020-05-01 20:04:21 +08004 * Copyright 2020 NXP
Prabhakar Kushwaha768e1202013-09-12 11:11:28 +05305 */
6
7#include <common.h>
8#include <command.h>
Simon Glass0af6e2d2019-08-01 09:46:52 -06009#include <env.h>
Simon Glass3bbe70c2019-12-28 10:44:54 -070010#include <fdt_support.h>
Prabhakar Kushwaha768e1202013-09-12 11:11:28 +053011#include <i2c.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060012#include <image.h>
Simon Glassa7b51302019-11-14 12:57:46 -070013#include <init.h>
Prabhakar Kushwaha768e1202013-09-12 11:11:28 +053014#include <netdev.h>
15#include <linux/compiler.h>
16#include <asm/mmu.h>
17#include <asm/processor.h>
18#include <asm/cache.h>
19#include <asm/immap_85xx.h>
20#include <asm/fsl_law.h>
21#include <asm/fsl_serdes.h>
Prabhakar Kushwaha768e1202013-09-12 11:11:28 +053022#include <asm/fsl_liodn.h>
23#include <fm_eth.h>
Zhao Qiang433e0af2014-03-21 16:21:46 +080024#include <hwconfig.h>
Prabhakar Kushwaha768e1202013-09-12 11:11:28 +053025
tang yuantian10871092014-12-18 10:20:07 +080026#include "../common/sleep.h"
Prabhakar Kushwaha768e1202013-09-12 11:11:28 +053027#include "../common/qixis.h"
28#include "t1040qds.h"
29#include "t1040qds_qixis.h"
30
31DECLARE_GLOBAL_DATA_PTR;
32
33int checkboard(void)
34{
35 char buf[64];
36 u8 sw;
37 struct cpu_type *cpu = gd->arch.cpu;
38 static const char *const freq[] = {"100", "125", "156.25", "161.13",
39 "122.88", "122.88", "122.88"};
40 int clock;
41
42 printf("Board: %sQDS, ", cpu->name);
43 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
44 QIXIS_READ(id), QIXIS_READ(arch));
45
46 sw = QIXIS_READ(brdcfg[0]);
47 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
48
49 if (sw < 0x8)
50 printf("vBank: %d\n", sw);
51 else if (sw == 0x8)
52 puts("PromJet\n");
53 else if (sw == 0x9)
54 puts("NAND\n");
55 else if (sw == 0x15)
56 printf("IFCCard\n");
57 else
58 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
59
60 printf("FPGA: v%d (%s), build %d",
61 (int)QIXIS_READ(scver), qixis_read_tag(buf),
62 (int)qixis_read_minor());
63 /* the timestamp string contains "\n" at the end */
64 printf(" on %s", qixis_read_time(buf));
65
66 /*
67 * Display the actual SERDES reference clocks as configured by the
68 * dip switches on the board. Note that the SWx registers could
69 * technically be set to force the reference clocks to match the
70 * values that the SERDES expects (or vice versa). For now, however,
71 * we just display both values and hope the user notices when they
72 * don't match.
73 */
74 puts("SERDES Reference: ");
75 sw = QIXIS_READ(brdcfg[2]);
76 clock = (sw >> 6) & 3;
77 printf("Clock1=%sMHz ", freq[clock]);
78 clock = (sw >> 4) & 3;
79 printf("Clock2=%sMHz\n", freq[clock]);
80
81 return 0;
82}
83
Biwen Li29cd2712020-05-01 20:04:21 +080084int select_i2c_ch_pca9547(u8 ch, int bus_num)
Prabhakar Kushwaha768e1202013-09-12 11:11:28 +053085{
86 int ret;
87
Biwen Li29cd2712020-05-01 20:04:21 +080088#ifdef CONFIG_DM_I2C
89 struct udevice *dev;
90
91 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
92 if (ret) {
93 printf("%s: Cannot find udev for a bus %d\n", __func__,
94 bus_num);
95 return ret;
96 }
97
98 ret = dm_i2c_write(dev, 0, &ch, 1);
99#else
Prabhakar Kushwaha768e1202013-09-12 11:11:28 +0530100 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
Biwen Li29cd2712020-05-01 20:04:21 +0800101#endif
Prabhakar Kushwaha768e1202013-09-12 11:11:28 +0530102 if (ret) {
103 puts("PCA: failed to select proper channel\n");
104 return ret;
105 }
106
107 return 0;
108}
109
Zhao Qiang433e0af2014-03-21 16:21:46 +0800110static void qe_board_setup(void)
111{
112 u8 brdcfg15, brdcfg9;
113
114 if (hwconfig("qe") && hwconfig("tdm")) {
115 brdcfg15 = QIXIS_READ(brdcfg[15]);
116 /*
117 * TDMRiser uses QE-TDM
118 * Route QE_TDM signals to TDM Riser slot
119 */
120 QIXIS_WRITE(brdcfg[15], brdcfg15 | 7);
121 } else if (hwconfig("qe") && hwconfig("uart")) {
122 brdcfg15 = QIXIS_READ(brdcfg[15]);
123 brdcfg9 = QIXIS_READ(brdcfg[9]);
124 /*
125 * Route QE_TDM signals to UCC
126 * ProfiBus controlled by UCC3
127 */
128 brdcfg15 &= 0xfc;
129 QIXIS_WRITE(brdcfg[15], brdcfg15 | 2);
130 QIXIS_WRITE(brdcfg[9], brdcfg9 | 4);
131 }
132}
133
tang yuantian10871092014-12-18 10:20:07 +0800134int board_early_init_f(void)
135{
136#if defined(CONFIG_DEEP_SLEEP)
137 if (is_warm_boot())
138 fsl_dp_disable_console();
139#endif
140
141 return 0;
142}
143
Prabhakar Kushwaha768e1202013-09-12 11:11:28 +0530144int board_early_init_r(void)
145{
146#ifdef CONFIG_SYS_FLASH_BASE
147 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
York Sun220c3462014-06-24 21:16:20 -0700148 int flash_esel = find_tlb_idx((void *)flashbase, 1);
Prabhakar Kushwaha768e1202013-09-12 11:11:28 +0530149
150 /*
151 * Remap Boot flash + PROMJET region to caching-inhibited
152 * so that flash can be erased properly.
153 */
154
155 /* Flush d-cache and invalidate i-cache of any FLASH data */
156 flush_dcache();
157 invalidate_icache();
158
York Sun220c3462014-06-24 21:16:20 -0700159 if (flash_esel == -1) {
160 /* very unlikely unless something is messed up */
161 puts("Error: Could not find TLB for FLASH BASE\n");
162 flash_esel = 2; /* give our best effort to continue */
163 } else {
164 /* invalidate existing TLB entry for flash + promjet */
165 disable_tlb(flash_esel);
166 }
Prabhakar Kushwaha768e1202013-09-12 11:11:28 +0530167
168 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
169 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
170 0, flash_esel, BOOKE_PAGESZ_256M, 1);
171#endif
Biwen Li29cd2712020-05-01 20:04:21 +0800172 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
Prabhakar Kushwaha768e1202013-09-12 11:11:28 +0530173
174 return 0;
175}
176
177unsigned long get_board_sys_clk(void)
178{
179 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
180
181 switch (sysclk_conf & 0x0F) {
182 case QIXIS_SYSCLK_64:
183 return 64000000;
184 case QIXIS_SYSCLK_83:
185 return 83333333;
186 case QIXIS_SYSCLK_100:
187 return 100000000;
188 case QIXIS_SYSCLK_125:
189 return 125000000;
190 case QIXIS_SYSCLK_133:
191 return 133333333;
192 case QIXIS_SYSCLK_150:
193 return 150000000;
194 case QIXIS_SYSCLK_160:
195 return 160000000;
196 case QIXIS_SYSCLK_166:
197 return 166666666;
198 }
199 return 66666666;
200}
201
202unsigned long get_board_ddr_clk(void)
203{
204 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
205
206 switch ((ddrclk_conf & 0x30) >> 4) {
207 case QIXIS_DDRCLK_100:
208 return 100000000;
209 case QIXIS_DDRCLK_125:
210 return 125000000;
211 case QIXIS_DDRCLK_133:
212 return 133333333;
213 }
214 return 66666666;
215}
216
Prabhakar Kushwaha768e1202013-09-12 11:11:28 +0530217#define NUM_SRDS_BANKS 2
218int misc_init_r(void)
219{
220 u8 sw;
221 serdes_corenet_t *srds_regs =
222 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
223 u32 actual[NUM_SRDS_BANKS] = { 0 };
224 int i;
225
226 sw = QIXIS_READ(brdcfg[2]);
227 for (i = 0; i < NUM_SRDS_BANKS; i++) {
228 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
229 switch (clock) {
230 case 0:
231 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
232 break;
233 case 1:
234 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
235 break;
236 case 2:
237 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
238 break;
239 }
240 }
241
242 puts("SerDes1");
243 for (i = 0; i < NUM_SRDS_BANKS; i++) {
244 u32 pllcr0 = srds_regs->bank[i].pllcr0;
245 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
246 if (expected != actual[i]) {
247 printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
248 i + 1, serdes_clock_to_string(expected),
249 serdes_clock_to_string(actual[i]));
250 }
251 }
252
Zhao Qiang433e0af2014-03-21 16:21:46 +0800253 qe_board_setup();
254
Prabhakar Kushwaha768e1202013-09-12 11:11:28 +0530255 return 0;
256}
257
Simon Glass2aec3cc2014-10-23 18:58:47 -0600258int ft_board_setup(void *blob, bd_t *bd)
Prabhakar Kushwaha768e1202013-09-12 11:11:28 +0530259{
260 phys_addr_t base;
261 phys_size_t size;
262
263 ft_cpu_setup(blob, bd);
264
Simon Glassda1a1342017-08-03 12:22:15 -0600265 base = env_get_bootm_low();
266 size = env_get_bootm_size();
Prabhakar Kushwaha768e1202013-09-12 11:11:28 +0530267
268 fdt_fixup_memory(blob, (u64)base, (u64)size);
269
270#ifdef CONFIG_PCI
271 pci_of_setup(blob, bd);
272#endif
273
274 fdt_fixup_liodn(blob);
275
276#ifdef CONFIG_HAS_FSL_DR_USB
Sriram Dash9fd465c2016-09-16 17:12:15 +0530277 fsl_fdt_fixup_dr_usb(blob, bd);
Prabhakar Kushwaha768e1202013-09-12 11:11:28 +0530278#endif
279
280#ifdef CONFIG_SYS_DPAA_FMAN
281 fdt_fixup_fman_ethernet(blob);
Prabhakar Kushwahae70cd8d2014-01-27 15:55:20 +0530282 fdt_fixup_board_enet(blob);
Prabhakar Kushwaha768e1202013-09-12 11:11:28 +0530283#endif
Simon Glass2aec3cc2014-10-23 18:58:47 -0600284
285 return 0;
Prabhakar Kushwaha768e1202013-09-12 11:11:28 +0530286}
287
288void qixis_dump_switch(void)
289{
290 int i, nr_of_cfgsw;
291
292 QIXIS_WRITE(cms[0], 0x00);
293 nr_of_cfgsw = QIXIS_READ(cms[1]);
294
295 puts("DIP switch settings dump:\n");
296 for (i = 1; i <= nr_of_cfgsw; i++) {
297 QIXIS_WRITE(cms[0], i);
298 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
299 }
300}
Prabhakar Kushwaha692256a2013-12-26 12:40:55 +0530301
302int board_need_mem_reset(void)
303{
304 return 1;
305}