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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Peter Howard9ed4f702015-03-23 09:19:56 +11002/*
3 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Based on da850evm.c. Original Copyrights follow:
6 *
7 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
8 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
Peter Howard9ed4f702015-03-23 09:19:56 +11009 */
10
11#include <common.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060012#include <env.h>
Peter Howard9ed4f702015-03-23 09:19:56 +110013#include <i2c.h>
Simon Glass97589732020-05-10 11:40:02 -060014#include <init.h>
Peter Howard9ed4f702015-03-23 09:19:56 +110015#include <net.h>
Peter Howard9ed4f702015-03-23 09:19:56 +110016#include <asm/arch/hardware.h>
17#include <asm/ti-common/davinci_nand.h>
18#include <asm/io.h>
Bartosz Golaszewskicdba2152019-07-29 08:58:09 +020019#include <ns16550.h>
20#include <dm/platdata.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090021#include <linux/errno.h>
Simon Glass0ffb9d62017-05-31 19:47:48 -060022#include <asm/mach-types.h>
Peter Howard9ed4f702015-03-23 09:19:56 +110023#include <asm/arch/davinci_misc.h>
Masahiro Yamadab2c88682017-01-10 13:32:07 +090024#ifdef CONFIG_MMC_DAVINCI
Peter Howard9ed4f702015-03-23 09:19:56 +110025#include <mmc.h>
26#include <asm/arch/sdmmc_defs.h>
27#endif
28
29DECLARE_GLOBAL_DATA_PTR;
30
31#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
32
Masahiro Yamadab2c88682017-01-10 13:32:07 +090033#ifdef CONFIG_MMC_DAVINCI
Peter Howard9ed4f702015-03-23 09:19:56 +110034/* MMC0 pin muxer settings */
35const struct pinmux_config mmc0_pins[] = {
36 /* GP0[11] is required for SD to work on Rev 3 EVMs */
37 { pinmux(0), 8, 4 }, /* GP0[11] */
38 { pinmux(10), 2, 0 }, /* MMCSD0_CLK */
39 { pinmux(10), 2, 1 }, /* MMCSD0_CMD */
40 { pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */
41 { pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */
42 { pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */
43 { pinmux(10), 2, 5 }, /* MMCSD0_DAT_3 */
44 /* LCDK supports only 4-bit mode, remaining pins are not configured */
45};
46#endif
47
48/* UART pin muxer settings */
49static const struct pinmux_config uart_pins[] = {
50 { pinmux(0), 4, 6 },
51 { pinmux(0), 4, 7 },
52 { pinmux(4), 2, 4 },
53 { pinmux(4), 2, 5 }
54};
55
56#ifdef CONFIG_DRIVER_TI_EMAC
57static const struct pinmux_config emac_pins[] = {
58 { pinmux(2), 8, 1 },
59 { pinmux(2), 8, 2 },
60 { pinmux(2), 8, 3 },
61 { pinmux(2), 8, 4 },
62 { pinmux(2), 8, 5 },
63 { pinmux(2), 8, 6 },
64 { pinmux(2), 8, 7 },
65 { pinmux(3), 8, 0 },
66 { pinmux(3), 8, 1 },
67 { pinmux(3), 8, 2 },
68 { pinmux(3), 8, 3 },
69 { pinmux(3), 8, 4 },
70 { pinmux(3), 8, 5 },
71 { pinmux(3), 8, 6 },
72 { pinmux(3), 8, 7 },
73 { pinmux(4), 8, 0 },
74 { pinmux(4), 8, 1 }
75};
76#endif /* CONFIG_DRIVER_TI_EMAC */
77
78/* I2C pin muxer settings */
79static const struct pinmux_config i2c_pins[] = {
80 { pinmux(4), 2, 2 },
81 { pinmux(4), 2, 3 }
82};
83
84#ifdef CONFIG_NAND_DAVINCI
85const struct pinmux_config nand_pins[] = {
86 { pinmux(7), 1, 1 },
87 { pinmux(7), 1, 2 },
88 { pinmux(7), 1, 4 },
89 { pinmux(7), 1, 5 },
90 { pinmux(8), 1, 0 },
91 { pinmux(8), 1, 1 },
92 { pinmux(8), 1, 2 },
93 { pinmux(8), 1, 3 },
94 { pinmux(8), 1, 4 },
95 { pinmux(8), 1, 5 },
96 { pinmux(8), 1, 6 },
97 { pinmux(8), 1, 7 },
98 { pinmux(9), 1, 0 },
99 { pinmux(9), 1, 1 },
100 { pinmux(9), 1, 2 },
101 { pinmux(9), 1, 3 },
102 { pinmux(9), 1, 4 },
103 { pinmux(9), 1, 5 },
104 { pinmux(9), 1, 6 },
105 { pinmux(9), 1, 7 },
106 { pinmux(12), 1, 5 },
107 { pinmux(12), 1, 6 }
108};
109
110#endif
111
112#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
113#define HAS_RMII 1
114#else
115#define HAS_RMII 0
116#endif
117
118const struct pinmux_resource pinmuxes[] = {
119 PINMUX_ITEM(uart_pins),
120 PINMUX_ITEM(i2c_pins),
121#ifdef CONFIG_NAND_DAVINCI
122 PINMUX_ITEM(nand_pins),
123#endif
124};
125
126const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
127
128const struct lpsc_resource lpsc[] = {
129 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
130 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
131 { DAVINCI_LPSC_EMAC }, /* image download */
132 { DAVINCI_LPSC_UART2 }, /* console */
133 { DAVINCI_LPSC_GPIO },
Masahiro Yamadab2c88682017-01-10 13:32:07 +0900134#ifdef CONFIG_MMC_DAVINCI
Peter Howard9ed4f702015-03-23 09:19:56 +1100135 { DAVINCI_LPSC_MMC_SD },
136#endif
137};
138
139const int lpsc_size = ARRAY_SIZE(lpsc);
140
141#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
142#define CONFIG_DA850_EVM_MAX_CPU_CLK 456000000
143#endif
144
145/*
146 * get_board_rev() - setup to pass kernel board revision information
147 * Returns:
148 * bit[0-3] Maximum cpu clock rate supported by onboard SoC
149 * 0000b - 300 MHz
150 * 0001b - 372 MHz
151 * 0010b - 408 MHz
152 * 0011b - 456 MHz
153 */
154u32 get_board_rev(void)
155{
156 return 0;
157}
158
159int board_early_init_f(void)
160{
161 /*
162 * Power on required peripherals
163 * ARM does not have access by default to PSC0 and PSC1
164 * assuming here that the DSP bootloader has set the IOPU
165 * such that PSC access is available to ARM
166 */
167 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
168 return 1;
169
170 return 0;
171}
172
173int board_init(void)
174{
Peter Howard9ed4f702015-03-23 09:19:56 +1100175 irq_init();
Peter Howard9ed4f702015-03-23 09:19:56 +1100176
Tom Rini48157342017-01-25 20:42:35 -0500177 /* arch number of the board */
178 gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_LCDK;
179
Peter Howard9ed4f702015-03-23 09:19:56 +1100180 /* address of boot parameters */
181 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
182
183
184 /* setup the SUSPSRC for ARM to control emulation suspend */
185 writel(readl(&davinci_syscfg_regs->suspsrc) &
186 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
187 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
188 DAVINCI_SYSCFG_SUSPSRC_UART2),
189 &davinci_syscfg_regs->suspsrc);
190
191 /* configure pinmux settings */
192 if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
193 return 1;
194
195#ifdef CONFIG_NAND_DAVINCI
196 /*
197 * NAND CS setup - cycle counts based on da850evm NAND timings in the
198 * Linux kernel @ 25MHz EMIFA
199 */
200 writel((DAVINCI_ABCR_WSETUP(15) |
201 DAVINCI_ABCR_WSTROBE(63) |
202 DAVINCI_ABCR_WHOLD(7) |
203 DAVINCI_ABCR_RSETUP(15) |
204 DAVINCI_ABCR_RSTROBE(63) |
205 DAVINCI_ABCR_RHOLD(7) |
206 DAVINCI_ABCR_TA(3) |
207 DAVINCI_ABCR_ASIZE_16BIT),
208 &davinci_emif_regs->ab2cr); /* CS3 */
209#endif
210
211
Masahiro Yamadab2c88682017-01-10 13:32:07 +0900212#ifdef CONFIG_MMC_DAVINCI
Peter Howard9ed4f702015-03-23 09:19:56 +1100213 if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0)
214 return 1;
215#endif
216
217#ifdef CONFIG_DRIVER_TI_EMAC
218 if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
219 return 1;
220 davinci_emac_mii_mode_sel(HAS_RMII);
221#endif /* CONFIG_DRIVER_TI_EMAC */
222
223 /* enable the console UART */
224 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
225 DAVINCI_UART_PWREMU_MGMT_UTRST),
226 &davinci_uart2_ctrl_regs->pwremu_mgmt);
227
228 return 0;
229}
230
Peter Howard9ed4f702015-03-23 09:19:56 +1100231#define CFG_MAC_ADDR_SPI_BUS 0
232#define CFG_MAC_ADDR_SPI_CS 0
233#define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
234#define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3
235
236#define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K)
237
238static int get_mac_addr(u8 *addr)
239{
240 /* Need to find a way to get MAC ADDRESS */
241 return 0;
242}
243
244void dsp_lpsc_on(unsigned domain, unsigned int id)
245{
246 dv_reg_p mdstat, mdctl, ptstat, ptcmd;
247 struct davinci_psc_regs *psc_regs;
248
249 psc_regs = davinci_psc0_regs;
250 mdstat = &psc_regs->psc0.mdstat[id];
251 mdctl = &psc_regs->psc0.mdctl[id];
252 ptstat = &psc_regs->ptstat;
253 ptcmd = &psc_regs->ptcmd;
254
255 while (*ptstat & (0x1 << domain))
256 ;
257
258 if ((*mdstat & 0x1f) == 0x03)
259 return; /* Already on and enabled */
260
261 *mdctl |= 0x03;
262
263 *ptcmd = 0x1 << domain;
264
265 while (*ptstat & (0x1 << domain))
266 ;
267 while ((*mdstat & 0x1f) != 0x03)
268 ; /* Probably an overkill... */
269}
270
271static void dspwake(void)
272{
273 unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
274
275 /* if the device is ARM only, return */
276 if ((REG(CHIP_REV_ID_REG) & 0x3f) == 0x10)
277 return;
278
Simon Glass64b723f2017-08-03 12:22:12 -0600279 if (!strcmp(env_get("dspwake"), "no"))
Peter Howard9ed4f702015-03-23 09:19:56 +1100280 return;
281
282 *resetvect++ = 0x1E000; /* DSP Idle */
283 /* clear out the next 10 words as NOP */
284 memset(resetvect, 0, sizeof(unsigned) * 10);
285
286 /* setup the DSP reset vector */
287 REG(HOST1CFG) = DAVINCI_L3CBARAM_BASE;
288
289 dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
290 REG(PSC0_MDCTL + (15 * 4)) |= 0x100;
291}
292
293#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
294/**
295 * rmii_hw_init
296 *
297 */
298int rmii_hw_init(void)
299{
300 return 0;
301}
302#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
303
304int misc_init_r(void)
305{
306 uint8_t tmp[20], addr[10];
307
308
Simon Glass64b723f2017-08-03 12:22:12 -0600309 if (env_get("ethaddr") == NULL) {
Peter Howard9ed4f702015-03-23 09:19:56 +1100310 /* Read Ethernet MAC address from EEPROM */
311 if (dvevm_read_mac_address(addr)) {
312 /* Set Ethernet MAC address from EEPROM */
313 davinci_sync_env_enetaddr(addr);
314 } else {
315 get_mac_addr(addr);
316 }
317
Fabien Parenteceb18f2016-11-10 17:16:35 +0100318 if (!is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr)) {
319 sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x",
320 addr[0], addr[1], addr[2], addr[3], addr[4],
321 addr[5]);
322
Simon Glass6a38e412017-08-03 12:22:09 -0600323 env_set("ethaddr", (char *)tmp);
Fabien Parenteceb18f2016-11-10 17:16:35 +0100324 } else {
Peter Howard9ed4f702015-03-23 09:19:56 +1100325 printf("Invalid MAC address read.\n");
Peter Howard9ed4f702015-03-23 09:19:56 +1100326 }
Peter Howard9ed4f702015-03-23 09:19:56 +1100327 }
Fabien Parenteceb18f2016-11-10 17:16:35 +0100328
Peter Howard9ed4f702015-03-23 09:19:56 +1100329#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
330 /* Select RMII fucntion through the expander */
331 if (rmii_hw_init())
332 printf("RMII hardware init failed!!!\n");
333#endif
334
335 dspwake();
336
337 return 0;
338}
339
Sekhar Norib8545762019-05-30 19:04:54 +0530340#if !CONFIG_IS_ENABLED(DM_MMC)
Masahiro Yamadab2c88682017-01-10 13:32:07 +0900341#ifdef CONFIG_MMC_DAVINCI
Peter Howard9ed4f702015-03-23 09:19:56 +1100342static struct davinci_mmc mmc_sd0 = {
343 .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
344 .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
345 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
Peter Howard9ed4f702015-03-23 09:19:56 +1100346};
347
348int board_mmc_init(bd_t *bis)
349{
350 mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
351
352 /* Add slot-0 to mmc subsystem */
353 return davinci_mmc_init(bis, &mmc_sd0);
354}
355#endif
Adam Fordd4df8142018-08-09 06:15:14 -0500356#endif
Bartosz Golaszewskicdba2152019-07-29 08:58:09 +0200357
358#ifdef CONFIG_SPL_BUILD
359static const struct ns16550_platdata serial_pdata = {
360 .base = DAVINCI_UART2_BASE,
361 .reg_shift = 2,
362 .clock = 228000000,
363 .fcr = UART_FCR_DEFVAL,
364};
365
366U_BOOT_DEVICE(omapl138_uart) = {
367 .name = "ns16550_serial",
368 .platdata = &serial_pdata,
369};
Bartosz Golaszewskif1412ef2019-11-14 16:10:30 +0100370
371U_BOOT_DEVICE(omapl138_mmc) = {
372 .name = "davinci_mmc",
373};
374
375void spl_board_init(void)
376{
377 davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins));
378}
Bartosz Golaszewskicdba2152019-07-29 08:58:09 +0200379#endif