| Simon Glass | 582ba6e | 2019-12-06 21:42:58 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright 2019 Google LLC |
| 4 | */ |
| 5 | |
| 6 | #ifndef _ASM_ARCH_UART_H |
| 7 | #define _ASM_ARCH_UART_H |
| 8 | |
| 9 | /** |
| 10 | * apl_uart_init() - Set up the APL UART device and clock |
| 11 | * |
| 12 | * This enables the PCI device, sets up the MMIO region and turns on the clock |
| 13 | * using LPSS. |
| 14 | * |
| 15 | * The UART won't actually work unless the GPIO settings are correct and the |
| 16 | * signals actually exit the SoC. See board_debug_uart_init() for that. |
| 17 | */ |
| 18 | int apl_uart_init(pci_dev_t bdf, ulong base); |
| 19 | |
| 20 | #endif |