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Tom Rini8b0c8a12018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrick Delaunay85b53972018-03-12 10:46:10 +01002/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
Patrick Delaunay85b53972018-03-12 10:46:10 +01004 */
5#include <common.h>
6#include <clk.h>
Simon Glass1d91ba72019-11-14 12:57:37 -07007#include <cpu_func.h>
Patrick Delaunay82168e82018-05-17 14:50:46 +02008#include <debug_uart.h>
Simon Glass5e6201b2019-08-01 09:46:51 -06009#include <env.h>
Simon Glass97589732020-05-10 11:40:02 -060010#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Patrick Delaunayf3674a42018-05-17 15:24:07 +020012#include <misc.h>
Simon Glass274e0b02020-05-10 11:39:56 -060013#include <net.h>
Patrick Delaunay85b53972018-03-12 10:46:10 +010014#include <asm/io.h>
15#include <asm/arch/stm32.h>
Patrick Delaunay01e3afe2018-03-19 19:09:21 +010016#include <asm/arch/sys_proto.h>
Patrick Delaunayf3674a42018-05-17 15:24:07 +020017#include <dm/device.h>
Patrick Delaunayc5d15652018-03-20 10:54:53 +010018#include <dm/uclass.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060019#include <linux/bitops.h>
Patrick Delaunay85b53972018-03-12 10:46:10 +010020
Patrick Delaunay58e95532018-03-19 19:09:20 +010021/* RCC register */
22#define RCC_TZCR (STM32_RCC_BASE + 0x00)
23#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
24#define RCC_BDCR (STM32_RCC_BASE + 0x0140)
25#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
Patrick Delaunayd4ca35c2019-02-27 17:01:26 +010026#define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
Patrick Delaunay58e95532018-03-19 19:09:20 +010027#define RCC_BDCR_VSWRST BIT(31)
28#define RCC_BDCR_RTCSRC GENMASK(17, 16)
29#define RCC_DBGCFGR_DBGCKEN BIT(8)
Patrick Delaunay85b53972018-03-12 10:46:10 +010030
Patrick Delaunay58e95532018-03-19 19:09:20 +010031/* Security register */
Patrick Delaunay85b53972018-03-12 10:46:10 +010032#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
33#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
34
35#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
36#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
37#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
38
39#define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
40
41#define PWR_CR1 (STM32_PWR_BASE + 0x00)
Fabien Dessenne9ebbdc92019-10-30 14:38:30 +010042#define PWR_MCUCR (STM32_PWR_BASE + 0x14)
Patrick Delaunay85b53972018-03-12 10:46:10 +010043#define PWR_CR1_DBP BIT(8)
Fabien Dessenne9ebbdc92019-10-30 14:38:30 +010044#define PWR_MCUCR_SBF BIT(6)
Patrick Delaunay85b53972018-03-12 10:46:10 +010045
Patrick Delaunay58e95532018-03-19 19:09:20 +010046/* DBGMCU register */
Patrick Delaunay01e3afe2018-03-19 19:09:21 +010047#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
Patrick Delaunay58e95532018-03-19 19:09:20 +010048#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
49#define DBGMCU_APB4FZ1_IWDG2 BIT(2)
Patrick Delaunay01e3afe2018-03-19 19:09:21 +010050#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
51#define DBGMCU_IDC_DEV_ID_SHIFT 0
52#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
53#define DBGMCU_IDC_REV_ID_SHIFT 16
Patrick Delaunay85b53972018-03-12 10:46:10 +010054
Patrick Delaunayd4ca35c2019-02-27 17:01:26 +010055/* GPIOZ registers */
56#define GPIOZ_SECCFGR 0x54004030
57
Patrick Delaunayc5d15652018-03-20 10:54:53 +010058/* boot interface from Bootrom
59 * - boot instance = bit 31:16
60 * - boot device = bit 15:0
61 */
62#define BOOTROM_PARAM_ADDR 0x2FFC0078
63#define BOOTROM_MODE_MASK GENMASK(15, 0)
64#define BOOTROM_MODE_SHIFT 0
65#define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
66#define BOOTROM_INSTANCE_SHIFT 16
67
Patrick Delaunay45c82d22019-02-27 17:01:13 +010068/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
69#define RPN_SHIFT 0
70#define RPN_MASK GENMASK(7, 0)
71
72/* Package = bit 27:29 of OTP16
73 * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
74 * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
75 * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
76 * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
77 * - others: Reserved
78 */
79#define PKG_SHIFT 27
80#define PKG_MASK GENMASK(2, 0)
81
Patrick Delaunay8e6985b2020-04-30 16:30:20 +020082/*
83 * early TLB into the .data section so that it not get cleared
84 * with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
85 */
86u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
87
Patrick Delaunay58e95532018-03-19 19:09:20 +010088#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
Patrick Delaunayf8fe21d2020-04-01 09:07:33 +020089#ifndef CONFIG_TFABOOT
Patrick Delaunay85b53972018-03-12 10:46:10 +010090static void security_init(void)
91{
92 /* Disable the backup domain write protection */
93 /* the protection is enable at each reset by hardware */
94 /* And must be disable by software */
95 setbits_le32(PWR_CR1, PWR_CR1_DBP);
96
97 while (!(readl(PWR_CR1) & PWR_CR1_DBP))
98 ;
99
100 /* If RTC clock isn't enable so this is a cold boot then we need
101 * to reset the backup domain
102 */
103 if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
104 setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
105 while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
106 ;
107 clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
108 }
109
110 /* allow non secure access in Write/Read for all peripheral */
111 writel(GENMASK(25, 0), ETZPC_DECPROT0);
112
113 /* Open SYSRAM for no secure access */
114 writel(0x0, ETZPC_TZMA1_SIZE);
115
116 /* enable TZC1 TZC2 clock */
117 writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
118
119 /* Region 0 set to no access by default */
120 /* bit 0 / 16 => nsaid0 read/write Enable
121 * bit 1 / 17 => nsaid1 read/write Enable
122 * ...
123 * bit 15 / 31 => nsaid15 read/write Enable
124 */
125 writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
126 /* bit 30 / 31 => Secure Global Enable : write/read */
127 /* bit 0 / 1 => Region Enable for filter 0/1 */
128 writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
129
130 /* Enable Filter 0 and 1 */
131 setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
132
133 /* RCC trust zone deactivated */
134 writel(0x0, RCC_TZCR);
135
136 /* TAMP: deactivate the internal tamper
137 * Bit 23 ITAMP8E: monotonic counter overflow
138 * Bit 20 ITAMP5E: RTC calendar overflow
139 * Bit 19 ITAMP4E: HSE monitoring
140 * Bit 18 ITAMP3E: LSE monitoring
141 * Bit 16 ITAMP1E: RTC power domain supply monitoring
142 */
143 writel(0x0, TAMP_CR1);
Patrick Delaunayd4ca35c2019-02-27 17:01:26 +0100144
145 /* GPIOZ: deactivate the security */
146 writel(BIT(0), RCC_MP_AHB5ENSETR);
147 writel(0x0, GPIOZ_SECCFGR);
Patrick Delaunay85b53972018-03-12 10:46:10 +0100148}
Patrick Delaunayf8fe21d2020-04-01 09:07:33 +0200149#endif /* CONFIG_TFABOOT */
Patrick Delaunay85b53972018-03-12 10:46:10 +0100150
Patrick Delaunay58e95532018-03-19 19:09:20 +0100151/*
Patrick Delaunay85b53972018-03-12 10:46:10 +0100152 * Debug init
Patrick Delaunay58e95532018-03-19 19:09:20 +0100153 */
Patrick Delaunay85b53972018-03-12 10:46:10 +0100154static void dbgmcu_init(void)
155{
156 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
157
158 /* Freeze IWDG2 if Cortex-A7 is in debug mode */
159 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
160}
161#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
162
Patrick Delaunayf8fe21d2020-04-01 09:07:33 +0200163#if !defined(CONFIG_TFABOOT) && \
Patrick Delaunay5d061412019-02-12 11:44:39 +0100164 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
Patrick Delaunay18660a62019-02-27 17:01:12 +0100165/* get bootmode from ROM code boot context: saved in TAMP register */
166static void update_bootmode(void)
167{
168 u32 boot_mode;
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100169 u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
170 u32 bootrom_device, bootrom_instance;
171
Patrick Delaunay18660a62019-02-27 17:01:12 +0100172 /* enable TAMP clock = RTCAPBEN */
173 writel(BIT(8), RCC_MP_APB5ENSETR);
174
175 /* read bootrom context */
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100176 bootrom_device =
177 (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
178 bootrom_instance =
179 (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
180 boot_mode =
181 ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
182 ((bootrom_instance << BOOT_INSTANCE_SHIFT) &
183 BOOT_INSTANCE_MASK);
184
185 /* save the boot mode in TAMP backup register */
186 clrsetbits_le32(TAMP_BOOT_CONTEXT,
187 TAMP_BOOT_MODE_MASK,
188 boot_mode << TAMP_BOOT_MODE_SHIFT);
Patrick Delaunay18660a62019-02-27 17:01:12 +0100189}
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100190#endif
Patrick Delaunay18660a62019-02-27 17:01:12 +0100191
192u32 get_bootmode(void)
193{
194 /* read bootmode from TAMP backup register */
195 return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
196 TAMP_BOOT_MODE_SHIFT;
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100197}
198
199/*
Patrick Delaunay8e6985b2020-04-30 16:30:20 +0200200 * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
201 * MMU/TLB is updated in enable_caches() for U-Boot after relocation
202 * or is deactivated in U-Boot entry function start.S::cpu_init_cp15
203 */
204static void early_enable_caches(void)
205{
206 /* I-cache is already enabled in start.S: cpu_init_cp15 */
207
208 if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
209 return;
210
211 gd->arch.tlb_size = PGTABLE_SIZE;
212 gd->arch.tlb_addr = (unsigned long)&early_tlb;
213
214 dcache_enable();
215
216 if (IS_ENABLED(CONFIG_SPL_BUILD))
217 mmu_set_region_dcache_behaviour(STM32_SYSRAM_BASE,
218 STM32_SYSRAM_SIZE,
219 DCACHE_DEFAULT_OPTION);
220 else
221 mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE,
222 DCACHE_DEFAULT_OPTION);
223}
224
225/*
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100226 * Early system init
227 */
Patrick Delaunay85b53972018-03-12 10:46:10 +0100228int arch_cpu_init(void)
229{
Patrick Delaunay82168e82018-05-17 14:50:46 +0200230 u32 boot_mode;
231
Patrick Delaunay8e6985b2020-04-30 16:30:20 +0200232 early_enable_caches();
233
Patrick Delaunay85b53972018-03-12 10:46:10 +0100234 /* early armv7 timer init: needed for polling */
235 timer_init();
236
237#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
238 dbgmcu_init();
Patrick Delaunayf8fe21d2020-04-01 09:07:33 +0200239#ifndef CONFIG_TFABOOT
Patrick Delaunay85b53972018-03-12 10:46:10 +0100240 security_init();
Patrick Delaunay18660a62019-02-27 17:01:12 +0100241 update_bootmode();
Patrick Delaunay85b53972018-03-12 10:46:10 +0100242#endif
Fabien Dessenne9ebbdc92019-10-30 14:38:30 +0100243 /* Reset Coprocessor state unless it wakes up from Standby power mode */
244 if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
245 writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
246 writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
247 }
Patrick Delaunay5d061412019-02-12 11:44:39 +0100248#endif
Patrick Delaunay82168e82018-05-17 14:50:46 +0200249
Patrick Delaunay82168e82018-05-17 14:50:46 +0200250 boot_mode = get_bootmode();
251
252 if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
253 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
254#if defined(CONFIG_DEBUG_UART) && \
Patrick Delaunayf8fe21d2020-04-01 09:07:33 +0200255 !defined(CONFIG_TFABOOT) && \
Patrick Delaunay82168e82018-05-17 14:50:46 +0200256 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
257 else
258 debug_uart_init();
259#endif
Patrick Delaunay85b53972018-03-12 10:46:10 +0100260
261 return 0;
262}
263
Patrick Delaunay58e95532018-03-19 19:09:20 +0100264void enable_caches(void)
265{
Patrick Delaunay8e6985b2020-04-30 16:30:20 +0200266 /* I-cache is already enabled in start.S: icache_enable() not needed */
267
268 /* deactivate the data cache, early enabled in arch_cpu_init() */
269 dcache_disable();
270 /*
271 * update MMU after relocation and enable the data cache
272 * warning: the TLB location udpated in board_f.c::reserve_mmu
273 */
Patrick Delaunay58e95532018-03-19 19:09:20 +0100274 dcache_enable();
275}
276
Patrick Delaunay01e3afe2018-03-19 19:09:21 +0100277static u32 read_idc(void)
278{
279 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
280
281 return readl(DBGMCU_IDC);
282}
283
Patrick Delaunay79bc6402020-03-18 09:24:48 +0100284u32 get_cpu_dev(void)
285{
286 return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
287}
288
Patrick Delaunay01e3afe2018-03-19 19:09:21 +0100289u32 get_cpu_rev(void)
290{
291 return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
292}
293
Patrick Delaunay45c82d22019-02-27 17:01:13 +0100294static u32 get_otp(int index, int shift, int mask)
295{
296 int ret;
297 struct udevice *dev;
298 u32 otp = 0;
299
300 ret = uclass_get_device_by_driver(UCLASS_MISC,
301 DM_GET_DRIVER(stm32mp_bsec),
302 &dev);
303
304 if (!ret)
305 ret = misc_read(dev, STM32_BSEC_SHADOW(index),
306 &otp, sizeof(otp));
307
308 return (otp >> shift) & mask;
309}
310
311/* Get Device Part Number (RPN) from OTP */
312static u32 get_cpu_rpn(void)
313{
314 return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
315}
316
Patrick Delaunay01e3afe2018-03-19 19:09:21 +0100317u32 get_cpu_type(void)
318{
Patrick Delaunay79bc6402020-03-18 09:24:48 +0100319 return (get_cpu_dev() << 16) | get_cpu_rpn();
Patrick Delaunay01e3afe2018-03-19 19:09:21 +0100320}
321
Patrick Delaunay45c82d22019-02-27 17:01:13 +0100322/* Get Package options from OTP */
Patrick Delaunayc74d6342019-07-05 17:20:13 +0200323u32 get_cpu_package(void)
Patrick Delaunay45c82d22019-02-27 17:01:13 +0100324{
325 return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
326}
327
Patrick Delaunay3e738f22020-02-12 19:37:43 +0100328void get_soc_name(char name[SOC_NAME_SIZE])
Patrick Delaunay85b53972018-03-12 10:46:10 +0100329{
Patrick Delaunay45c82d22019-02-27 17:01:13 +0100330 char *cpu_s, *cpu_r, *pkg;
Patrick Delaunay01e3afe2018-03-19 19:09:21 +0100331
Patrick Delaunay45c82d22019-02-27 17:01:13 +0100332 /* MPUs Part Numbers */
Patrick Delaunay01e3afe2018-03-19 19:09:21 +0100333 switch (get_cpu_type()) {
Patrick Delaunaydb33b0e2020-02-26 11:26:43 +0100334 case CPU_STM32MP157Fxx:
335 cpu_s = "157F";
336 break;
337 case CPU_STM32MP157Dxx:
338 cpu_s = "157D";
339 break;
Patrick Delaunay45c82d22019-02-27 17:01:13 +0100340 case CPU_STM32MP157Cxx:
341 cpu_s = "157C";
342 break;
343 case CPU_STM32MP157Axx:
344 cpu_s = "157A";
345 break;
Patrick Delaunaydb33b0e2020-02-26 11:26:43 +0100346 case CPU_STM32MP153Fxx:
347 cpu_s = "153F";
348 break;
349 case CPU_STM32MP153Dxx:
350 cpu_s = "153D";
351 break;
Patrick Delaunay45c82d22019-02-27 17:01:13 +0100352 case CPU_STM32MP153Cxx:
353 cpu_s = "153C";
354 break;
355 case CPU_STM32MP153Axx:
356 cpu_s = "153A";
357 break;
Patrick Delaunaydb33b0e2020-02-26 11:26:43 +0100358 case CPU_STM32MP151Fxx:
359 cpu_s = "151F";
360 break;
361 case CPU_STM32MP151Dxx:
362 cpu_s = "151D";
363 break;
Patrick Delaunay45c82d22019-02-27 17:01:13 +0100364 case CPU_STM32MP151Cxx:
365 cpu_s = "151C";
366 break;
367 case CPU_STM32MP151Axx:
368 cpu_s = "151A";
369 break;
370 default:
371 cpu_s = "????";
372 break;
373 }
374
375 /* Package */
376 switch (get_cpu_package()) {
377 case PKG_AA_LBGA448:
378 pkg = "AA";
379 break;
380 case PKG_AB_LBGA354:
381 pkg = "AB";
382 break;
383 case PKG_AC_TFBGA361:
384 pkg = "AC";
385 break;
386 case PKG_AD_TFBGA257:
387 pkg = "AD";
Patrick Delaunay01e3afe2018-03-19 19:09:21 +0100388 break;
389 default:
Patrick Delaunay45c82d22019-02-27 17:01:13 +0100390 pkg = "??";
Patrick Delaunay01e3afe2018-03-19 19:09:21 +0100391 break;
392 }
393
Patrick Delaunay45c82d22019-02-27 17:01:13 +0100394 /* REVISION */
Patrick Delaunay01e3afe2018-03-19 19:09:21 +0100395 switch (get_cpu_rev()) {
396 case CPU_REVA:
397 cpu_r = "A";
398 break;
399 case CPU_REVB:
400 cpu_r = "B";
401 break;
Patrick Delaunayc8d4afe2020-01-28 10:11:06 +0100402 case CPU_REVZ:
403 cpu_r = "Z";
404 break;
Patrick Delaunay01e3afe2018-03-19 19:09:21 +0100405 default:
406 cpu_r = "?";
407 break;
408 }
409
Patrick Delaunay3e738f22020-02-12 19:37:43 +0100410 snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r);
411}
412
413#if defined(CONFIG_DISPLAY_CPUINFO)
414int print_cpuinfo(void)
415{
416 char name[SOC_NAME_SIZE];
417
418 get_soc_name(name);
419 printf("CPU: %s\n", name);
Patrick Delaunay85b53972018-03-12 10:46:10 +0100420
421 return 0;
422}
423#endif /* CONFIG_DISPLAY_CPUINFO */
424
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100425static void setup_boot_mode(void)
426{
Patrick Delaunay18660a62019-02-27 17:01:12 +0100427 const u32 serial_addr[] = {
428 STM32_USART1_BASE,
429 STM32_USART2_BASE,
430 STM32_USART3_BASE,
431 STM32_UART4_BASE,
432 STM32_UART5_BASE,
433 STM32_USART6_BASE,
434 STM32_UART7_BASE,
435 STM32_UART8_BASE
436 };
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100437 char cmd[60];
438 u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
439 u32 boot_mode =
440 (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
Patrick Delaunay1b03eb02019-06-21 15:26:39 +0200441 unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
Patrick Delaunay008d3c32019-02-27 17:01:20 +0100442 u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
Patrick Delaunay18660a62019-02-27 17:01:12 +0100443 struct udevice *dev;
444 int alias;
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100445
Patrick Delaunay008d3c32019-02-27 17:01:20 +0100446 pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
447 __func__, boot_ctx, boot_mode, instance, forced_mode);
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100448 switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
449 case BOOT_SERIAL_UART:
Patrick Delaunay18660a62019-02-27 17:01:12 +0100450 if (instance > ARRAY_SIZE(serial_addr))
451 break;
452 /* serial : search associated alias in devicetree */
453 sprintf(cmd, "serial@%x", serial_addr[instance]);
454 if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev))
455 break;
456 if (fdtdec_get_alias_seq(gd->fdt_blob, "serial",
457 dev_of_offset(dev), &alias))
458 break;
459 sprintf(cmd, "%d", alias);
460 env_set("boot_device", "serial");
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100461 env_set("boot_instance", cmd);
Patrick Delaunay18660a62019-02-27 17:01:12 +0100462
463 /* restore console on uart when not used */
464 if (gd->cur_serial_dev != dev) {
465 gd->flags &= ~(GD_FLG_SILENT |
466 GD_FLG_DISABLE_CONSOLE);
467 printf("serial boot with console enabled!\n");
468 }
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100469 break;
470 case BOOT_SERIAL_USB:
471 env_set("boot_device", "usb");
472 env_set("boot_instance", "0");
473 break;
474 case BOOT_FLASH_SD:
475 case BOOT_FLASH_EMMC:
476 sprintf(cmd, "%d", instance);
477 env_set("boot_device", "mmc");
478 env_set("boot_instance", cmd);
479 break;
480 case BOOT_FLASH_NAND:
481 env_set("boot_device", "nand");
482 env_set("boot_instance", "0");
483 break;
Patrick Delaunayb5a7ca22020-03-18 09:22:52 +0100484 case BOOT_FLASH_SPINAND:
485 env_set("boot_device", "spi-nand");
486 env_set("boot_instance", "0");
487 break;
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100488 case BOOT_FLASH_NOR:
489 env_set("boot_device", "nor");
490 env_set("boot_instance", "0");
491 break;
492 default:
493 pr_debug("unexpected boot mode = %x\n", boot_mode);
494 break;
495 }
Patrick Delaunay008d3c32019-02-27 17:01:20 +0100496
497 switch (forced_mode) {
498 case BOOT_FASTBOOT:
499 printf("Enter fastboot!\n");
500 env_set("preboot", "env set preboot; fastboot 0");
501 break;
502 case BOOT_STM32PROG:
503 env_set("boot_device", "usb");
504 env_set("boot_instance", "0");
505 break;
506 case BOOT_UMS_MMC0:
507 case BOOT_UMS_MMC1:
508 case BOOT_UMS_MMC2:
509 printf("Enter UMS!\n");
510 instance = forced_mode - BOOT_UMS_MMC0;
511 sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
512 env_set("preboot", cmd);
513 break;
514 case BOOT_RECOVERY:
515 env_set("preboot", "env set preboot; run altbootcmd");
516 break;
517 case BOOT_NORMAL:
518 break;
519 default:
520 pr_debug("unexpected forced boot mode = %x\n", forced_mode);
521 break;
522 }
523
524 /* clear TAMP for next reboot */
525 clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
Patrick Delaunayf3674a42018-05-17 15:24:07 +0200526}
527
528/*
529 * If there is no MAC address in the environment, then it will be initialized
530 * (silently) from the value in the OTP.
531 */
Marek Vasut187cae22019-12-18 16:52:19 +0100532__weak int setup_mac_address(void)
Patrick Delaunayf3674a42018-05-17 15:24:07 +0200533{
534#if defined(CONFIG_NET)
535 int ret;
536 int i;
537 u32 otp[2];
538 uchar enetaddr[6];
539 struct udevice *dev;
540
541 /* MAC already in environment */
542 if (eth_env_get_enetaddr("ethaddr", enetaddr))
543 return 0;
544
545 ret = uclass_get_device_by_driver(UCLASS_MISC,
546 DM_GET_DRIVER(stm32mp_bsec),
547 &dev);
548 if (ret)
549 return ret;
550
Patrick Delaunay10263a52019-02-27 17:01:29 +0100551 ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC),
Patrick Delaunayf3674a42018-05-17 15:24:07 +0200552 otp, sizeof(otp));
Simon Glass587dc402018-11-06 15:21:39 -0700553 if (ret < 0)
Patrick Delaunayf3674a42018-05-17 15:24:07 +0200554 return ret;
555
556 for (i = 0; i < 6; i++)
557 enetaddr[i] = ((uint8_t *)&otp)[i];
558
559 if (!is_valid_ethaddr(enetaddr)) {
Manivannan Sadhasivame5237722019-05-02 13:26:45 +0530560 pr_err("invalid MAC address in OTP %pM\n", enetaddr);
Patrick Delaunayf3674a42018-05-17 15:24:07 +0200561 return -EINVAL;
562 }
563 pr_debug("OTP MAC address = %pM\n", enetaddr);
564 ret = !eth_env_set_enetaddr("ethaddr", enetaddr);
565 if (!ret)
566 pr_err("Failed to set mac address %pM from OTP: %d\n",
567 enetaddr, ret);
568#endif
569
570 return 0;
571}
572
573static int setup_serial_number(void)
574{
575 char serial_string[25];
576 u32 otp[3] = {0, 0, 0 };
577 struct udevice *dev;
578 int ret;
579
580 if (env_get("serial#"))
581 return 0;
582
583 ret = uclass_get_device_by_driver(UCLASS_MISC,
584 DM_GET_DRIVER(stm32mp_bsec),
585 &dev);
586 if (ret)
587 return ret;
588
Patrick Delaunay10263a52019-02-27 17:01:29 +0100589 ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL),
Patrick Delaunayf3674a42018-05-17 15:24:07 +0200590 otp, sizeof(otp));
Simon Glass587dc402018-11-06 15:21:39 -0700591 if (ret < 0)
Patrick Delaunayf3674a42018-05-17 15:24:07 +0200592 return ret;
593
Patrick Delaunayaf5564a2019-02-27 17:01:25 +0100594 sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
Patrick Delaunayf3674a42018-05-17 15:24:07 +0200595 env_set("serial#", serial_string);
596
597 return 0;
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100598}
599
600int arch_misc_init(void)
601{
602 setup_boot_mode();
Patrick Delaunayf3674a42018-05-17 15:24:07 +0200603 setup_mac_address();
604 setup_serial_number();
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100605
606 return 0;
607}