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git01.mediatek.com / filogic / uboot / 1a25236f2ab5689bdafafbe255419ea75730d786 / . / arch / arm / include / asm / arch-lpc32xx / config.h
blob: f7a698e72dee393539dd5656f38a8de6635e27b2 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]2/*
3 * Common definitions for LPC32XX board configurations
4 *
Vladimir Zapolskiydb6a14f2015-02-12 00:24:20 +0200[diff] [blame]5 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]6 */
7
8#ifndef _LPC32XX_CONFIG_H
9#define _LPC32XX_CONFIG_H
10
Vladimir Zapolskiydb6a14f2015-02-12 00:24:20 +0200[diff] [blame]11
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]12/* Basic CPU architecture */
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]13#define CONFIG_ARCH_CPU_INIT
14
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]15/* UART configuration */
Vladimir Zapolskiy8bf94502015-12-19 23:29:25 +0200[diff] [blame]16#if (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]17 (CONFIG_SYS_LPC32XX_UART == 7)
Vladimir Zapolskiy8bf94502015-12-19 23:29:25 +0200[diff] [blame]18#if !defined(CONFIG_LPC32XX_HSUART)
19#define CONFIG_LPC32XX_HSUART
20#endif
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]21#endif
22
Vladimir Zapolskiy8bf94502015-12-19 23:29:25 +0200[diff] [blame]23#if !defined(CONFIG_SYS_NS16550_CLK)
24#define CONFIG_SYS_NS16550_CLK 13000000
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]25#endif
Vladimir Zapolskiy8bf94502015-12-19 23:29:25 +0200[diff] [blame]26
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]27#define CONFIG_SYS_BAUDRATE_TABLE \
28 { 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
29
Albert ARIBAUD \(3ADEV\)391e1632015-03-31 11:40:43 +0200[diff] [blame]30/* Ethernet */
31#define LPC32XX_ETH_BASE ETHERNET_BASE
32
Vladimir Zapolskiya6e30ef2015-08-11 19:57:09 +0300[diff] [blame]33/* NAND */
34#if defined(CONFIG_NAND_LPC32XX_SLC)
35#define NAND_LARGE_BLOCK_PAGE_SIZE 0x800
36#define NAND_SMALL_BLOCK_PAGE_SIZE 0x200
37
38#if !defined(CONFIG_SYS_NAND_PAGE_SIZE)
39#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE
40#endif
41
42#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE)
43#define CONFIG_SYS_NAND_OOBSIZE 64
44#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
45 48, 49, 50, 51, 52, 53, 54, 55, \
46 56, 57, 58, 59, 60, 61, 62, 63, }
47#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
48#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE)
49#define CONFIG_SYS_NAND_OOBSIZE 16
50#define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, }
51#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
52#else
53#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value"
54#endif
55
56#define CONFIG_SYS_NAND_ECCSIZE 0x100
57#define CONFIG_SYS_NAND_ECCBYTES 3
58#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
59 CONFIG_SYS_NAND_PAGE_SIZE)
60#endif /* CONFIG_NAND_LPC32XX_SLC */
61
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]62/* NOR Flash */
63#if defined(CONFIG_SYS_FLASH_CFI)
64#define CONFIG_FLASH_CFI_DRIVER
65#define CONFIG_SYS_FLASH_PROTECTION
66#endif
67
Vladimir Zapolskiy69ec0752015-08-12 20:32:08 +0300[diff] [blame]68/* USB OHCI */
69#if defined(CONFIG_USB_OHCI_LPC32XX)
70#define CONFIG_USB_OHCI_NEW
71#define CONFIG_SYS_USB_OHCI_CPU_INIT
72#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
73#define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE
74#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lpc32xx-ohci"
75#endif
76
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]77#endif /* _LPC32XX_CONFIG_H */